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AD9744ACPZRL71中文資料亞德諾數(shù)據(jù)手冊(cè)PDF規(guī)格書

AD9744ACPZRL71
廠商型號(hào)

AD9744ACPZRL71

功能描述

14-Bit, 210 MSPS TxDAC? D/A Converter

文件大小

1.32553 Mbytes

頁(yè)面數(shù)量

32 頁(yè)

生產(chǎn)廠商 Analog Devices
企業(yè)簡(jiǎn)稱

AD亞德諾

中文名稱

亞德諾半導(dǎo)體技術(shù)有限公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2024-11-20 18:22:00

AD9744ACPZRL71規(guī)格書詳情

GENERAL DESCRIPTION

The AD9744 is a 14-bit resolution, wideband, third generation member of the TxDAC series of high performance, low power CMOS digital-to-analog converters (DACs). The TxDAC family,

consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs, is specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface options, small outline package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. The AD9744 offers exceptional ac and dc performance while supporting update rates up to 210 MSPS.

FEATURES

High performance member of pin-compatible

TxDAC product family

Excellent spurious-free dynamic range performance

SFDR to Nyquist

83 dBc at 5 MHz output

80 dBc at 10 MHz output

73 dBc at 20 MHz output

SNR at 5 MHz output, 125 MSPS: 77 dB

Twos complement or straight binary data format

Differential current outputs: 2 mA to 20 mA

Power dissipation: 135 mW at 3.3 V

Power-down mode: 15 mW at 3.3 V

On-chip 1.2 V reference

CMOS-compatible digital interface

28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP packages

Edge-triggered latches

APPLICATIONS

Wideband communication transmit channel

Direct IFs

Base stations

Wireless local loops

Digital radio links

Direct digital synthesis (DDS)

Instrumentation

DC SPECIFICATIONS

TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫(kù)存 備注 價(jià)格
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