AD9761集成電路（IC）的數(shù)模轉(zhuǎn)換器（DAC）規(guī)格書PDF中文資料

AD9761屬于集成電路（IC）的數(shù)模轉(zhuǎn)換器（DAC）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9761數(shù)模轉(zhuǎn)換器（DAC）數(shù)模轉(zhuǎn)換器（DAC、D/A、D2A 或 D 轉(zhuǎn) A）可將數(shù)字信號轉(zhuǎn)換為緩沖或無緩沖的模擬電壓或電流。DAC 架構(gòu)是否適合特定應(yīng)用，要取決于分辨率和采樣頻率。DAC 通常用于音樂播放器，將數(shù)字數(shù)據(jù)流轉(zhuǎn)換為模擬音頻流。它們還用于電視和手機，將數(shù)字視頻數(shù)據(jù)轉(zhuǎn)換為模擬視頻信號，再連接到屏幕驅(qū)動器，以顯示單色或彩色圖像。

PRODUCT DESCRIPTION

The AD9761 is a complete dual-channel, high speed, 10-bit CMOS DAC. The AD9761 has been developed specifcally for use in wide bandwidth communication applications (e.g., spread spectrum) where digital I and Q information is being processed during transmit operations. It integrates two 10-bit, 40 MSPS DACs, dual 2x interpolation flters, a voltage reference, and digi tal input interface circuitry. The AD9761 supports a 20 MSPS per channel input data rate that is then interpolated by 2x up to 40 MSPS before simultaneously updating each DAC.

The interleaved I and Q input data stream is presented to the digital interface circuitry, which consists of I and Q latches as well as some additional control logic. The data is de-interleaved back into its original I and Q data. An on-chip state machine ensures the proper pairing of I and Q data. The data output from each latch is then processed by a 2x digital interpolation flter that eases the reconstruction flter requirements. The interpolated output of each flter serves as the input of their respective 10-bit DAC.

FEATURES

Complete 10-Bit, 40 MSPS Dual Transmit DAC

Excellent Gain and Offset Matching

Differential Nonlinearity Error: 0.5 LSB

Effective Number of Bits: 9.5

Signal-to-Noise and Distortion Ratio: 59 dB

Spurious-Free Dynamic Range: 71 dB

2x Interpolation Filters

20 MSPS/Channel Data Rate

Single Supply: 3 V to 5.5 V

Low Power Dissipation: 93 mW (3 V Supply @

40 MSPS)

On-Chip Reference

28-Lead SSOP