AD9773BSV集成電路（IC）的數(shù)模轉(zhuǎn)換器（DAC）規(guī)格書(shū)PDF中文資料

AD9773BSV屬于集成電路（IC）的數(shù)模轉(zhuǎn)換器（DAC）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9773BSV數(shù)模轉(zhuǎn)換器（DAC）數(shù)模轉(zhuǎn)換器（DAC、D/A、D2A 或 D 轉(zhuǎn) A）可將數(shù)字信號(hào)轉(zhuǎn)換為緩沖或無(wú)緩沖的模擬電壓或電流。DAC 架構(gòu)是否適合特定應(yīng)用，要取決于分辨率和采樣頻率。DAC 通常用于音樂(lè)播放器，將數(shù)字?jǐn)?shù)據(jù)流轉(zhuǎn)換為模擬音頻流。它們還用于電視和手機(jī)，將數(shù)字視頻數(shù)據(jù)轉(zhuǎn)換為模擬視頻信號(hào)，再連接到屏幕驅(qū)動(dòng)器，以顯示單色或彩色圖像。

GENERAL DESCRIPTION

The AD9773 is the 12-bit member of the AD977x pin compatible, high performance, programmable 2×/4×/8× interpolating TxDAC+? family. The AD977x family features

a serial port interface (SPI) that provides a high level of programmability, thus allowing for enhanced system-level options. These options include selectable 2×/4×/8× interpolation filters; fS/2, fS/4, or fS/8 digital quadrature modulation with image rejection; a direct IF mode; programmable channel gain and offset control; programmable internal clock divider;

straight binary or twos complement data interface; and a single port or dual-port data interface.

The selectable 2×/4×/8× interpolation filters simplify the requirements of the reconstruction filters while simultaneously enhancing the TxDAC+ family’s pass-band noise/distortion

performance. The independent channel gain and offset adjust registers allow the user to calibrate LO feedthrough and side band suppression errors associated with analog quadrature

modulators. The 6 dB of gain adjustment range can also be used to control the output power level of each DAC.

FEATURES

12-bit resolution, 160 MSPS/400 MSPS

input/output data rate

Selectable 2×/4×/8× interpolating filter

Programmable channel gain and offset adjustment

fS/2, fS/4, fS/8 digital quadrature modulation capabilit

Direct IF transmission mode for 70 MHz + IFs

Enables image rejection architecture

Fully compatible SPI port

Excellent ac performance

SFDR ?69 dBc @ 2 MHz to 35 MHz

WCDMA ACPR ?69 dB @ IF = 19.2 MHz

Internal PLL clock multiplier

Selectable internal clock divider

Versatile clock input

Differential/single-ended sine wave or

TTL/CMOS/LVPECL compatible

Versatile input data interface

Twos complement/straight binary data coding

Dual-port or single-port interleaved input data

Single 3.3 V supply operation

Power dissipation: typical 1.2 W @ 3.3 V

On-chip 1.2 V reference

80-lead thin quad flat package, exposed pad (TQFP_EP)

APPLICATIONS

Communications

Analog quadrature modulation architecture

3G, multicarrier GSM, TDMA, CDMA systems

Broadband wireless, point-to-point microwave radios

Instrumentation/ATE