AD9958BCPZ集成電路（IC）的直接數(shù)字合成（DDS）規(guī)格書PDF中文資料

AD9958BCPZ屬于集成電路（IC）的直接數(shù)字合成（DDS）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9958BCPZ直接數(shù)字合成（DDS）直接數(shù)字合成 (DDS) 用于由數(shù)字信號(hào)生成不同頻率的模擬波形。在必須大范圍掃描的無線系統(tǒng)中可用于頻率控制。主時(shí)鐘頻率有 5MHz、16MHz、16.776MHz、25MHz、50MHz、75MHz、125MHz、180MHz、200MHz、250MHz、300MHz、400MHz、500MHz、1GHz、2.5GHz 和 3GHz，分辨率為 10 b、12 b 或 14 b。

GENERAL DESCRIPTION

The AD9958 consists of two DDS cores that provide indepen dent frequency, phase, and amplitude control on each channel. This flexibility can be used to correct imbalances between signals due to analog processing, such as filtering, amplification, or PCB layout related mismatches. Because both channels share

a common system clock, they are inherently synchronized. Synchronization of multiple devices is supported.

FEATURES

2 synchronized DDS channels @ 500 MSPS

Independent frequency/phase/amplitude control between channels

Matched latencies for frequency/phase/amplitude changes

Excellent channel-to-channel isolation (>72 dB)

Linear frequency/phase/amplitude sweeping capability

Up to 16 levels of frequency/phase/amplitude modulation (pin-selectable)

2 integrated 10-bit digital-to-analog converters (DACs)

Individually programmable DAC full-scale currents

0.12 Hz or better frequency tuning resolution

14-bit phase offset resolution

10-bit output amplitude scaling resolution

Serial I/O port interface (SPI) with 800 Mbps data throughput

Software-/hardware-controlled power-down

Dual supply operation (1.8 V DDS core/3.3 V serial I/O)

Multiple device synchronization

Selectable 4× to 20× REFCLK multiplier (PLL)

Selectable REFCLK crystal oscillator

56-lead LFCSP

APPLICATIONS

Agile local oscillators

Phased array radars/sonars

Instrumentation

Synchronized clocking

RF source for AOTF

Single-side band suppressed carriers

Quadrature communications