ADAU1702JSTZ集成電路（IC）的DSP（數(shù)字信號(hào)處理器）規(guī)格書PDF中文資料

ADAU1702JSTZ屬于集成電路（IC）的DSP（數(shù)字信號(hào)處理器）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的ADAU1702JSTZDSP（數(shù)字信號(hào)處理器）數(shù)字信號(hào)處理器是類似于微處理器或微控制器的器件，但區(qū)別在于其內(nèi)部架構(gòu)經(jīng)修改，適用于對(duì)連續(xù)數(shù)據(jù)流連續(xù)執(zhí)行以乘法和加法運(yùn)算為主的算法，而不是以條件邏輯或大量并發(fā)進(jìn)程為主的算法。該器件通常用于諸如音頻或視頻信號(hào)處理等應(yīng)用。

GENERAL DESCRIPTION

The ADAU1702 is a complete single-chip audio system with a 28-/56-bit audio DSP, ADCs, DACs, and microcontroller-like control interfaces. Signal processing includes equalization, cross over, bass enhancement, multiband dynamics processing, delay compensation, speaker compensation, and stereo image widening and can be used to compensate for real-world limitations of speakers, amplifiers, and listening environments, providing a dramatic improvements of perceived audio quality.

FEATURES

28-/56-bit, 25 MIPS digital audio processor

Two ADCs: SNR of 100 dB, THD + N of ?83 dB

Four DACs: SNR of 104 dB, THD + N of ?90 dB

Complete standalone operation

Self-boot from serial EEPROM

Auxiliary ADC with 4-input mux for analog control

GPIOs for digital controls and outputs

Fully programmable with SigmaStudio? graphical tool

28-bit × 28-bit multiplier with 56-bit accumulator for full double-precision processing

Clock oscillator for generating master clock from crystal

PLL for generating master clock from 64 × fS, 256 × fS, 384 × fS, or 512 × fS clocks

Flexible serial data input/output ports with I2S-compatible, left-justified, right-justified, and TDM modes

Sampling rates up to 192 kHz supported

On-chip voltage regulator for compatibility with 3.3 V systems

48-lead, plastic LQFP

APPLICATIONS

Multimedia speaker systems

MP3 player speaker docks

Automotive head units

Minicomponent stereos

Digital televisions

Studio monitors

Speaker crossovers

Musical instrument effects processors

In-seat sound systems (aircraft/motor coaches)