ADC12DJ5200SE_V01中文資料德州儀器數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

1 Features

? ADC core:

– 12-bit resolution

– Up to 10.4 GSPS in single-channel mode

– Up to 5.2 GSPS in dual-channel mode

? Single Ended 50 Ω Inputs:

– Analog input range (–3 dB): 2 to 6.3 GHz

– Full-scale input power (4.5 GHz): - 1.25 dBm

– Flexible VCM: AC coupled with no DC path to

GND or supply

? Performance specifications:

– Noise floor (2.3 GHz, –20 dBFS,

INPUTFS = 1.5 dBm):

? Dual-channel mode: –149 dBFS/Hz

? Single-channel mode: –151.5 dBFS/Hz

– ENOB (dual channel, FIN = 2.3 GHz): 8.5 Bits

? Noiseless aperture delay (tAD) adjustment:

– Precise sampling control: 19-fs Step

– Simplifies synchronization and interleaving

– Temperature and voltage invariant delays

? Easy-to-use synchronization features:

– Automatic SYSREF timing calibration

– Timestamp for sample marking

? JESD204C serial data interface:

– Maximum lane rate: 17.16 Gbps

– Support for 64b/66b and 8b/10b encoding

– 8b/10b modes are JESD204B compatible

? Optional digital down-converters (DDC):

– 4x, 8x, 16x and 32x complex decimation

– Four independent 32-Bit NCOs per DDC

? Peak RF Input Power: +26.25 dBm (+ 27.5 dBFS,

560x fullscale power)

? Programmable FIR filter for equalization

? Power consumption: 4 W

? Power supplies: 1.1 V, 1.9 V

2 Applications

? Communications testers (802.11ad, 5G)

? Electronic warfare (SIGINT, ELINT)

? Satellite communications (SATCOM)

? RF-sampling software-defined radio (SDR)

3 Description

The ADC12DJ5200SE is an RF-sampling, gigasample,

analog-to-digital converter (ADC) with

integrated input baluns. The ADC12DJ5200SE can

be configured as a dual-channel, 5.2 GSPS ADC or

single-channel, 10.4 GSPS ADC. The -3 dB input

frequency range of 2 to 6.3 GHz enables direct RF

sampling of S-band and C-band for frequency agile

systems.

The ADC12DJ5200SE uses a high-speed JESD204C

output interface with up to 16 serialized lanes

supporting up to 17.16 Gbps line rate. Deterministic

latency and multi-device synchronization is supported

through JESD204C subclass-1. The JESD204C

interface can be configured to trade-off line rate and

number of lanes. Both 8b/10b and 64b/66b data

encoding schemes are supported. 64b/66b encoding

supports forward error correction (FEC) for improved

bit error rates. The interface is backwards compatible

with JESD204B receivers.

Innovative synchronization features, including

noiseless aperture delay adjustment and SYSREF

windowing, simplify system design for multi-channel

applications. Optional digital down converters (DDCs)

are available to provide digital conversion to

baseband and to reduce the interface rate. A

programmable FIR filter allows on-chip equalization.