ADC12QJ1600ALRSEP中文資料德州儀器數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

1 Features

? Radiation Tolerance:

– Total Ionizing Dose (TID): 30 krad (Si)

– Single Event Latchup (SEL): 43 MeV-cm2/mg

– Single Event Upset (SEU) immune registers

? Space-enhanced plastic (space EP):

– Meets ASTM E595 outgassing specification

– Vendor item drawing (VID) V62/22610

– Temperature range: –55°C to 125°C

– One fabrication, assembly, and test site

– Wafer lot traceability

– Extended product life cycle

– Extended product change notification

? ADC Core:

– Resolution: 12 Bit

– Maximum sampling rate: 1.6 GSPS

– Non-interleaved architecture

– Internal dither reduces high-order harmonics

? Performance specifications (–1 dBFS):

– SNR (100 MHz): 57.4 dBFS

– ENOB (100 MHz): 9.1 Bits

– SFDR (100 MHz): 64 dBc

– Noise floor (–20 dBFS): –147 dBFS

? Full-scale input voltage: 800 mVPP-DIFF

? Full-power input bandwidth: 6 GHz

? JESD204C Serial data interface:

– Support for 2 to 8 total SerDes lanes

– Maximum baud-rate: 17.16 Gbps

– 64B/66B and 8B/10B encoding modes

– Subclass-1 support for deterministic latency

– Compatible with JESD204B receivers

? Optional internal sampling clock generation

– Internal PLL and VCO (7.2–8.2 GHz)

? SYSREF Windowing eases synchronization

? Four clock outputs simplify system clocking

– Reference clocks for FPGA or adjacent ADC

– Reference clock for SerDes transceivers

? Timestamp input and output for pulsed systems

? Power consumption (1 GSPS): 1.9 W

? Power supplies: 1.1 V, 1.9 V

2 Applications

? Electronic warfare (SIGINT, ELINT)

? Satellite communications (SATCOM)

3 Description

ADC12QJ1600-SEP is a quad channel, 12-bit, 1.6

GSPS analog-to-digital converters (ADC). Low power

consumption, high sampling rate and 12-bit resolution

makes the device suited for a variety of mulch-chanel

communications systems.

Full-power input bandwidth (-3 dB) of 6 GHz enables

direct RF sampling of L-band and S-band.

A number of clocking features are included to relax

system hardware requirements, such as an internal

phase-locked loop (PLL) with integrated voltagecontrolled

oscillator (VCO) to generate the sampling

clock. Four clock outputs are provided to clock the

logic and SerDes of the FPGA or ASIC. A timestamp

input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size

by reducing the amount of printed circuit board (PCB)

routing. Interface modes support from 2 to 8 lanes

(dual and quad channel devices) or 1 to 4 lanes (for

the single channel device), with SerDes baud-rates up

to 17.16 Gbps, to allow the optimal configuration for

each application.