ADC34RF55IRTD中文資料德州儀器數(shù)據(jù)手冊(cè)PDF規(guī)格書

1 Features

? 14-Bit, quad channel 3-GSPS ADC

? Max output rate: 1.5-GSPS

? Noise spectral density:

– -156 dBFS/Hz without averaging

– -158 dBFS/Hz with 2x averaging

? Single core (non-interleaved) ADC architecture

? Aperture jitter: 50 fs

? Low close-in residual phase noise:

– -127 dBc/Hz at 10 kHz offset

? Spectral performance (fIN = 0.9 GHz, -4 dBFS):

– 2x internal averaging

– SNR: 62.3 dBFS

– SFDR HD2,3: 63 dBc

– SFDR worst spur: 85 dBFS

? Spectral performance (fIN = 1.8 GHz, -4 dBFS):

– 2x internal averaging

– SNR: 63 dBFS

– SFDR HD2,3: 68 dBc

– SFDR worst spur: 86 dBFS

? Input full scale: 1.1, 1.35 Vpp (2, 3.5 dBm)

? Code error rate (CER): 10-15

? Full power input bandwidth (-3 dB): 2.75 GHz

? JESD204B serial data interface

– Maximum lane rate: 13 Gbps

– Supports subclass 1 deterministic latency

? Digital down-converters

– Up to two DDC per ADC channel

– Complex output: 4x to 128x decimation

– 48-bit NCO phase coherent frequency hopping

– Fast frequency hopping: < 1 μs

? Power consumption: 1.2 W/channel

? Power supplies: 1.8 V, 1.2 V

2 Applications

? Phased array radar

? Software defined radio (SDR)

? Spectrum analyzer

? High-speed digitizer

? Cable infrastructure

? Electronic warfare

? Communications infrastructure

3 Description

The ADC34RF55 is a single core 14-bit, 3-GSPS,

quad channel analog to digital converters (ADC) that

support RF sampling with input frequencies up to

3 GHz. The design maximizes signal-to-noise ratio

(SNR), and delivers a noise spectral density of -156

dBFS/Hz. Using additional internal ADCs along with

on-chip signal averaging, the noise density improves

to -158 dBFS/Hz.

Each ADC channel can be connected to a dual-band

digital down-converter (DDC) using a 48-bit NCO

which supports phase coherent frequency hopping.

Using the GPIO pins for NCO frequency control,

frequency hopping can be achieved in less than 1 μs.

The devices supports the JESD204B serial data

interface with subclass 1 deterministic latency using

data rates up to 13Gbps. There are only 2 serdes

lanes per ADC channel. Therefore, in bypass mode,

the maximum output data rate supported is 1.5GSPS.

When using faster ADC sampling rates on chip,

decimation is required.

The power efficient ADC architecture consumes

1.2W/ch and provides power scaling with lower

sampling rates.