ADC3543IRSBR中文資料德州儀器數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

1 Features

? 14-bit 10/25/65 MSPS ADC

? Noise floor: –155 dBFS/Hz

? Ultra-low power with optimized power scaling:

35 mW (10 MSPS) to 84 mW (65 MSPS)

? Latency: 1 clock cycle

? INL: ±0.6 LSB; DNL: ±0.1 LSB

? Reference: external or internal

? Input Bandwidth: 900 MHz (3-dB)

? Industrial temperature range: –40°C to +105°C

? On-chip digital filter (optional)

– Decimation by 2, 4, 8, 16, 32

– 32-bit NCO

? SDR/DDR and Serial CMOS interface

? Small footprint: 40-WQFN (5 mm × 5 mm) package

? Single 1.8-V supply

? Spectral Performance (fIN = 10 MHz):

– SNR: 79.0 dBFS

– SFDR: 87 dBc HD2, HD3

– SFDR: 99 dBFS Worst Spur

? Spectral Performance (fIN = 64 MHz):

– SNR: 78.0 dBFS

– SFDR: 70 dBc HD2, HD3

– SFDR: 91 dBFS Worst Spur

1 Features

? 14-bit 10/25/65 MSPS ADC

? Noise floor: –155 dBFS/Hz

? Ultra-low power with optimized power scaling:

35 mW (10 MSPS) to 84 mW (65 MSPS)

? Latency: 1 clock cycle

? INL: ±0.6 LSB; DNL: ±0.1 LSB

? Reference: external or internal

? Input Bandwidth: 900 MHz (3-dB)

? Industrial temperature range: –40°C to +105°C

? On-chip digital filter (optional)

– Decimation by 2, 4, 8, 16, 32

– 32-bit NCO

? SDR/DDR and Serial CMOS interface

? Small footprint: 40-WQFN (5 mm × 5 mm) package

? Single 1.8-V supply

? Spectral Performance (fIN = 10 MHz):

– SNR: 79.0 dBFS

– SFDR: 87 dBc HD2, HD3

– SFDR: 99 dBFS Worst Spur

? Spectral Performance (fIN = 64 MHz):

– SNR: 78.0 dBFS

– SFDR: 70 dBc HD2, HD3

– SFDR: 91 dBFS Worst Spur

3 Description

The ADC3541, ADC3542 and ADC3543 (ADC354x)

family of devices are low-noise, ultra-low power,

14-bit, 10 to 65-MSPS, high-speed analog-todigital

converters (ADCs). Designed for low power

consumption, these devices deliver a noise spectral

density of –155 dBFS/Hz. The ADC354x offers great

dc precision together with IF sampling support,

which make these devices an excellent choice for a

wide range of applications. High-speed control loops

benefit from the short latency of only one clock cycle.

The ADC consumes only 79 mW at 65 MSPS, and

the power consumption scales very well with lower

sampling rates.

The ADC354x uses an SDR, DDR or a serial

CMOS interface to output the data offering the lowest

power digital interface, together with the flexibility

to minimize the number of digital interconnects.

These devices are a pin-to-pin compatible family with

different speed grades. These devices support the

extended industrial temperature range of –40°C to

+105?C.