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ADC3668中文資料德州儀器數(shù)據(jù)手冊PDF規(guī)格書

ADC3668
廠商型號

ADC3668

功能描述

ADC364x Dual-Channel, 14-Bit 250MSPS and 500MSPS Analog-to-Digital Converter (ADC)

文件大小

4.42179 Mbytes

頁面數(shù)量

85

生產(chǎn)廠商 Texas Instruments
企業(yè)簡稱

TI1德州儀器

中文名稱

德州儀器官網(wǎng)

原廠標識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2025-5-4 11:10:00

人工找貨

ADC3668價格和庫存,歡迎聯(lián)系客服免費人工找貨

ADC3668規(guī)格書詳情

1 Features

? 14-bit, dual channel 250 and 500MSPS ADC

? Noise spectral density: -158.5dBFS/Hz

? Thermal Noise: 74.5dBFS

? Single core (non-interleaved) ADC architecture

? Power consumption:

– 300mW/channel (500MSPS)

– 250mW/channel (250MSPS)

? Aperture jitter: 75fs

? Buffered analog inputs

– Programmable 100Ω to 200Ω termination

? Input full scale: 2Vpp

? Full power input bandwidth (-3dB): 1.4GHz

? Spectral performance (fIN = 70MHz, -1dBFS):

– SNR: 73.8dBFS

– SFDR HD2,3: 84dBc

– SFDR worst spur: 90dBFS

? Digital down-converters (DDCs)

– Up to four independent DDCs

– Complex and real decimation

– Decimation: /2, /4 to /32768 decimation

– 48-bit NCO phase coherent frequency hopping

? DDR, Serial LVDS interface

– 14-bit Parallel DDR LVDS for DDC bypass

– 16-bit Serial LVDS for decimation

– 32-bit output option for high decimation

2 Applications

? Software defined radio

? Spectrum analyzer

? Radar

? Spectroscopy

? Power amplifier linearization

? Communications infrastructure

3 Description

The ADC3648 and ADC3649 (ADC364x) are a 14-

bit, 250MSPS and 500MSPS, dual channel analog to

digital converter (ADC). The devices are designed for

high signal-to-noise ratio (SNR) and deliver a noise

spectral density of -158.5dBFS/Hz (500MSPS).

The power efficient ADC architecture consumes

300mW/ch at 500MSPS and provides power scaling

with lower sampling rates (250mW/ch at 250MSPS).

The ADC364x includes an optional quad band

digital down-converter (DDC) supporting wide band

decimation by 2 to narrow band decimation by 32768.

The DDC uses a 48-bit NCO which supports phase

coherent and phase continuous frequency hopping.

The ADC364x is outfitted with a flexible LVDS

interface. In decimation bypass mode, the device

uses a 14-bit wide parallel DDR LVDS interface.

When using decimation, the output data is transmitted

using a serial LVDS interface reducing the number

of lanes needed as decimation increases. For high

decimation rates, the output resolution can be

increased to 32-bit.

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