ADCLK846BCPZ-REEL7集成電路（IC）的時鐘緩沖器驅動器規(guī)格書PDF中文資料

ADCLK846BCPZ-REEL7屬于集成電路（IC）的時鐘緩沖器驅動器。由亞德諾半導體技術有限公司制造生產的ADCLK846BCPZ-REEL7時鐘緩沖器，驅動器時鐘緩沖器和驅動器集成電路產品族中的產品用于幫助信號在系統(tǒng)中傳輸，常用作頻率/時間參考信號，以同步系統(tǒng)內的活動。盡管這些器件最常用到的功能就是緩沖（即，為使信號不受驅動負載的影響而從某個信號源復制信號），但是該產品族中的某些器件還能執(zhí)行其他功能，例如選擇性改變緩沖信號路徑、按某個整數(shù)值分割信號頻率，或進行所用電信號格式轉換。

CIRCUIT DESCRIPTION

The circuit in Figure 1 was constructed by connecting the respective evaluation boards for the individual products. Connections were made with matched cable lengths. The first of three basic requirements to synchronize multiple AD9910’s is to provide a co-incident reference clock (REF CLK).

The setup uses the AD9520 as the REF CLK source for each AD9910 DDS. The AD9520 runs off an external crystal and the internal PLL. The AD9520 distributes phase aligned 1 GHz REF CLKs (PECL outputs) to all four AD9910 evaluation boards. It also provides a CMOS output clock to the Tektronix DG2020A data pattern generator for the IO_UPDATE.

CIRCUIT FUNCTION AND BENEFITS

Synchronization of multiple DDS devices allows precise digital tuning control of the phase and amplitude across multiple frequency carriers. This type of control is useful in radar applications and quadrature (I/Q) upconversion for side-band suppression.

The circuit in Figure 1 demonstrates how to synchronize four AD9910 1 GSPS, DDS chips using the AD9520 clock generator and the ADCLK846 clock fanout buffer. The result is precise phase alignment between the clock and output signals of four AD9910 devices.