ADF4108BCPZ集成電路（IC）的時鐘發(fā)生器PLL頻率合成器規(guī)格書PDF中文資料

ADF4108BCPZ屬于集成電路（IC）的時鐘發(fā)生器PLL頻率合成器。由亞德諾半導體技術有限公司制造生產(chǎn)的ADF4108BCPZ時鐘發(fā)生器，PLL，頻率合成器時鐘發(fā)生器、PLL 和頻率合成器集成電路 (IC) 可為邏輯器件提供參考信號的穩(wěn)定定時脈沖，這些器件包括計算機、微控制器、數(shù)據(jù)通信系統(tǒng)和圖形/視頻發(fā)生器。這些集成電路可能包括緩沖器、驅動器、分頻器、倍頻器、多路復用器、合成器、扇出分配器和預分頻器。

GENERAL DESCRIPTION

The ADF4108 frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost.

FEATURES

8.0 GHz bandwidth

3.2 V to 3.6 V power supply

Separate charge pump supply (VP) allows extended tuning voltage in 3.3 V systems

Programmable, dual modulus prescaler 8/9, 16/17, 32/33, or 64/65

Programmable charge pump currents

Programmable antibacklash pulse width

3-wire serial interface

Analog and digital lock detect

Hardware and software power-down mode

Loop filter design possible with ADIsimPLL

APPLICATIONS

Broadband wireless access

Satellite systems

Instrumentation

Wireless LANs

Base stations for wireless radio