ADF4156BRUZ集成電路（IC）的時(shí)鐘發(fā)生器PLL頻率合成器規(guī)格書PDF中文資料

ADF4156BRUZ屬于集成電路（IC）的時(shí)鐘發(fā)生器PLL頻率合成器。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的ADF4156BRUZ時(shí)鐘發(fā)生器，PLL，頻率合成器時(shí)鐘發(fā)生器、PLL 和頻率合成器集成電路 (IC) 可為邏輯器件提供參考信號的穩(wěn)定定時(shí)脈沖，這些器件包括計(jì)算機(jī)、微控制器、數(shù)據(jù)通信系統(tǒng)和圖形/視頻發(fā)生器。這些集成電路可能包括緩沖器、驅(qū)動器、分頻器、倍頻器、多路復(fù)用器、合成器、扇出分配器和預(yù)分頻器。

GENERAL DESCRIPTION

The ADF4156 is a 6 GHz fractional-N frequency synthesizer that implements local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a sigma-delta (Σ-Δ) based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). The RF output phase is programmable for applications that require a particular phase relationship between the output and the reference. The ADF4156 also features cycle slip reduction circuitry leading to faster lock times without the

need for modifications to the loop filter.

FEATURES

RF bandwidth to 6 GHz

2.7 V to 3.3 V power supply

Separate VP allows extended tuning voltage

Programmable fractional modulus

Programmable charge pump currents

3-wire serial interface

Digital lock detect

Power-down mode

Pin compatible with

ADF4110/ADF4111/ADF4112/ADF4113/ADF4106/

ADF4153 and ADF4154 frequency synthesizers

Programmable RF output phase

Loop filter design possible with ADISimPLL

Cycle slip reduction for faster lock times

APPLICATIONS

CATV equipment

Base stations for mobile radio (WiMAX, GSM, PCS, DCS,

SuperCell 3G, CDMA, WCDMA)

Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)

Wireless LANs, PMR

Communications test equipment