GENERAL DESCRIPTION

The ADF4193 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations. It consists of a low noise, digital phase frequency detector (PFD), and a precision differential charge pump. There is also a differential amplifier to convert the differential charge pump output to a single-ended voltage for the external voltage-controlled oscillator (VCO).

FEATURES

New, fast settling, fractional-N PLL architecture

Single PLL replaces ping-pong synthesizers

Frequency hop across GSM band in 5 μs with phase settled

by 20 μs

0.5° rms phase error at 2 GHz RF output

Digitally programmable output phase

RF input range up to 3.5 GHz

3-wire serial interface

On-chip, low noise differential amplifier

Phase noise figure of merit: ?216 dBc/Hz

Loop filter design possible using ADIsimPLL

Qualified for automotive applications

APPLICATIONS

GSM/EDGE base stations

PHS base stations

Instrumentation and test equipment

ADF4193BCPZ屬于集成電路（IC） > 時(shí)鐘發(fā)生器，PLL，頻率合成器。亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的ADF4193BCPZ時(shí)鐘發(fā)生器，PLL，頻率合成器時(shí)鐘發(fā)生器、PLL 和頻率合成器集成電路 (IC) 可為邏輯器件提供參考信號(hào)的穩(wěn)定定時(shí)脈沖，這些器件包括計(jì)算機(jī)、微控制器、數(shù)據(jù)通信系統(tǒng)和圖形/視頻發(fā)生器。這些集成電路可能包括緩沖器、驅(qū)動(dòng)器、分頻器、倍頻器、多路復(fù)用器、合成器、扇出分配器和預(yù)分頻器。