ADF4382BCCZ中文資料亞德諾數(shù)據(jù)手冊PDF規(guī)格書

FEATURES

? Output frequency range: 687.5 MHz to 22 GHz

? Integrated RMS jitter at 20 GHz = 20 fs (integration bandwidth:

100 Hz to 100 MHz)

? Integrated RMS jitter at 20 GHz = 31 fs (ADC SNR method)

? VCO fast calibration time < 1 μs

? VCO autocalibration time < 100 μs

? Phase noise floor: ?156 dBc/Hz at 20 GHz

? PLL specifications

? ?239 dBc/Hz: normalized in-band phase noise floor

? ?287 dBc/Hz: normalized 1/f phase noise floor

? 625 MHz maximum phase/frequency detector input frequency

? 4.5 GHz reference input frequency

? Typical spurious fPFD: ?90 dBc

? Reference to output delay specifications

? Propagation delay temperature coefficient: 0.06 ps/°C

? Adjustment step size: <1 ps

? Multichip output phase alignment

? 3.3 V and 5 V power supplies

? ADIsimPLL? loop filter design tool support

? 7 mm × 7 mm, 48-terminal LGA

? ?40°C to +105°C operating temperature

APPLICATIONS

? High performance data converter clocking

? Wireless infrastructure (MC-GSM, 5G, 6G)

? Test and measurement