ADN2817ACPZ-RL集成電路（IC）的應(yīng)用特定時(shí)鐘/定時(shí)規(guī)格書PDF中文資料

ADN2817ACPZ-RL屬于集成電路（IC）的應(yīng)用特定時(shí)鐘/定時(shí)。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的ADN2817ACPZ-RL應(yīng)用特定時(shí)鐘/定時(shí)專用時(shí)鐘和計(jì)時(shí) IC（集成電路）產(chǎn)品族中的產(chǎn)品主要用于執(zhí)行與時(shí)間或頻率信息生成和分配相關(guān)的各種操作，適合的設(shè)計(jì)環(huán)境較特定，例如 AMD 和 Intel 的中央處理單元 (CPU) 或圖形處理單元 (GPU)、DVD 音頻設(shè)備、藍(lán)光光盤播放器、以太網(wǎng)設(shè)備、PCIe、SATA、光纖通道接口、車載娛樂總線等。

GENERAL DESCRIPTION

The ADN2817/ADN2818 provide the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 10 Mbps to 2.7 Gbps. The ADN2817/ADN2818 automatically lock to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are exceeded, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for ?40°C to +85°C ambient temperature, unless otherwise noted.

FEATURES

Serial data input: 10 Mbps to 2.7 Gbps

Exceeds ITU-T jitter specifications

Integrated limiting amplifier

5 mV p-p sensitivity (ADN2817 only)

Adjustable slice level: ±100 mV (ADN2817 only)

Patented dual-loop clock recovery architecture

Programmable LOS detect (ADN2817 only)

Integrated PRBS generator and detector

No reference clock required

Loss of lock indicator

Supports double data rate

Bit error rate monitor (BERMON) or sample phase adjust options

Rate selectivity without the use of a reference clock

I2C interface to access optional features

Single-supply operation: 3.3 V

Low power

650 mW (ADN2817)

600 mW (ADN2818)

5 mm × 5 mm 32-lead LFCSP

APPLICATIONS

SONET OC-1, OC-3, OC-12, OC-48, and all associated FEC rates

Fibre Channel, 2× Fibre Channel, GbE, HDTV

WDM transponders

Regenerators/repeaters

Test equipment