ADN2913_V01中文資料亞德諾數(shù)據(jù)手冊PDF規(guī)格書

FEATURES

Serial data input: 6.5 Mbps to 8.5 Gbps

No reference clock required

Exceeds SONET/SDH requirements for jitter transfer/ generation/tolerance

Quantizer sensitivity: 6.3 mV typical (limiting amplifier mode)

Optional limiting amplifier, equalizer (EQ), and 0 dB EQ inputs

Programmable jitter transfer bandwidth to support G.8251 OTN

Programmable slice level

Sample phase adjust (5.65 Gbps or greater)

Output polarity invert

Programmable LOS threshold via I2C

I2C interface to access optional features

Loss of signal (LOS) alarm (limiting amplifier mode only)

Loss of lock (LOL) indicator

PRBS generator/detector

Application aware power

352 mW at 8.5 Gbps, equalizer mode, no clock output

380 mW at 6.144 Gbps, limiting amplifier mode, no clock output

340 mW at 622 Mbps, 0 dB EQ mode, no clock output

Power supplies: 1.2 V, flexible 1.8 V to 3.3 V, and 3.3 V

4 mm × 4 mm, 24-lead LFCSP

APPLICATIONS

SONET/SDH OC-1/OC-3/OC-12/OC-48 and all associated FEC rates

1GE, 1GFC, 2GFC, 4GFC, 8GFC, CPRI OS/L.6 up to OS/L.60

Any rate regenerators/repeaters