ADN4670集成電路（IC）的時(shí)鐘緩沖器驅(qū)動(dòng)器規(guī)格書PDF中文資料

ADN4670屬于集成電路（IC）的時(shí)鐘緩沖器驅(qū)動(dòng)器。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的ADN4670時(shí)鐘緩沖器，驅(qū)動(dòng)器時(shí)鐘緩沖器和驅(qū)動(dòng)器集成電路產(chǎn)品族中的產(chǎn)品用于幫助信號(hào)在系統(tǒng)中傳輸，常用作頻率/時(shí)間參考信號(hào)，以同步系統(tǒng)內(nèi)的活動(dòng)。盡管這些器件最常用到的功能就是緩沖（即，為使信號(hào)不受驅(qū)動(dòng)負(fù)載的影響而從某個(gè)信號(hào)源復(fù)制信號(hào)），但是該產(chǎn)品族中的某些器件還能執(zhí)行其他功能，例如選擇性改變緩沖信號(hào)路徑、按某個(gè)整數(shù)值分割信號(hào)頻率，或進(jìn)行所用電信號(hào)格式轉(zhuǎn)換。

GENERAL DESCRIPTION

The ADN4670 is a low voltage differential signaling (LVDS) clock driver that expands a differential clock input signal to 10 differential clock outputs. The device is programmable using a simple serial interface, so that one of two clock inputs can be selected (CLK0/CLK0 or CLK1/CLK1) and any of the differential outputs (Q0/Q0 to Q9/Q9) can be enabled or disabled (tristated). The ADN4670 is designed for use in 50 ? transmission line environments.

When the enable input EN is high, the device may be programmed by clocking 11 data bits into the shift register. The first 10 bits determine which outputs are enabled (0 = disabled, 1 = enabled), while the 11th bit selects the clock input (0 = CLK0, 1 = CLK1). A 12th clock pulse transfers data from the shift register to the control register.

The ADN4670 is fully specified over the industrial temperature range and is available in a 32-lead LFCSP and LQFP packages.

FEATURES

Low output skew <30 ps (typical)

Distributes one differential clock input to 10 LVDS clock outputs

Programmable—one of two differential clock inputs can be selected (CLK0, CLK1) and individual differential clock outputs enabled/disabled

Signaling rate up to 1.1 GHz (typical)

2.375 V to 2.625 V power supply range

±100 mV differential input threshold

Input common-mode range from rail-to-rail

I/O pins fail-safe during power-down: VDD = 0 V

Available in 32-lead LFCSP and LQFP packages

Industrial operating temperature range: ?40°C to +85°C

APPLICATIONS

Clock distribution networks