ADP5034-2-EVALZ中文資料亞德諾數(shù)據(jù)手冊PDF規(guī)格書

GENERAL DESCRIPTION

The ADP5034 combines two high performance buck regulators and two low dropout (LDO) regulators. It is available in either a 24-lead 4 mm × 4 mm LFCSP or a 28-lead TSSOP package.

The high switching frequency of the buck regulators enables tiny multilayer external components and minimizes the board space.

When the MODE pin is set to high, the buck regulators operate in forced PWM mode. When the MODE pin is set to low, the buck regulators operate in PWM mode when the load is above a predefined threshold. When the load current falls below a predefined threshold, the regulator operates in power save mode (PSM), improving the light load efficiency.

The two bucks operate out of phase to reduce the input capacitor requirement. The low quiescent current, low dropout voltage, and wide input voltage range of the ADP5034 LDOs extend the battery life of portable devices. The ADP5034 LDOs maintain power supply rejection greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage.

Regulators in the ADP5034 are activated through dedicated enable pins. The default output voltages can be externally set in the adjustable version, or factory programmable to a wide range of preset values in the fixed voltage version.

FEATURES

Main input voltage range: 2.3 V to 5.5 V

Two 1200 mA buck regulators and two 300 mA LDOs

24-lead, 4 mm × 4 mm LFCSP or 28-lead TSSOP package

Regulator accuracy: ±1.8

Factory programmable or external adjustable VOUTx

3 MHz buck operation with forced PWM and auto PWM/PSM modes

BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V

LDO1/LDO2: output voltage range from 0.8 V to 5.2 V

LDO1/LDO2: input supply voltage from 1.7 V to 5.5 V

LDO1/LDO2: high PSRR and low output noise

APPLICATIONS

Power for processors, ASICS, FPGAs, and RF chipsets

Portable instrumentation and medical devices

Space constrained devices