ADSP-21160NCBZ-100集成電路（IC）的DSP（數(shù)字信號處理器）規(guī)格書PDF中文資料

ADSP-21160NCBZ-100屬于集成電路（IC）的DSP（數(shù)字信號處理器）。由亞德諾半導體技術(shù)有限公司制造生產(chǎn)的ADSP-21160NCBZ-100DSP（數(shù)字信號處理器）數(shù)字信號處理器是類似于微處理器或微控制器的器件，但區(qū)別在于其內(nèi)部架構(gòu)經(jīng)修改，適用于對連續(xù)數(shù)據(jù)流連續(xù)執(zhí)行以乘法和加法運算為主的算法，而不是以條件邏輯或大量并發(fā)進程為主的算法。該器件通常用于諸如音頻或視頻信號處理等應用。

GENERAL DESCRIPTION

The ADSP-21160x SHARC? DSP family has two members: ADSP-21160M and ADSP-21160N. The ADSP-21160M is fabricated in a 0.25 micron CMOS process. The ADSP-21160N is fabricated in a 0.18 micron CMOS process. The ADSP-21160N offers higher performance and lower power consumption than the ADSP-21160M. Easing portability, the ADSP-21160x is application source code compatible with first generation ADSP-2106x SHARC DSPs in SISD (single instruction, single data) mode. To take advantage of the processor’s SIMD (singleinstruction, multiple-data) capability, some code changes are needed. Like other SHARC DSPs, the ADSP-21160x is a 32-bit processor that is optimized for high performance DSP applications. The ADSP-21160x includes a core running up to 100 MHz, a dual-ported on-chip SRAM, an integrated I/O processor with multiprocessing support, and multiple internal buses to eliminate I/O bottlenecks.

SUMMARY

High performance 32-bit DSP—applications in audio,

medical, military, graphics, imaging, and communication

Super Harvard architecture—4 independent buses for dual

data fetch, instruction fetch, and nonintrusive, zero-overhead I/O

Backward compatible—assembly source level compatible

with code for ADSP-2106x DSPs

Single-instruction, multiple-data (SIMD) computational

architecture—two 32-bit IEEE floating-point computation

units, each with a multiplier, ALU, shifter, and register file

Integrated peripherals—integrated I/O processor, 4M bits

on-chip dual-ported SRAM, glueless multiprocessing

features, and ports (serial, link, external bus, and JTAG)