ADSP-21375集成電路（IC）的DSP（數(shù)字信號處理器）規(guī)格書PDF中文資料

ADSP-21375屬于集成電路（IC）的DSP（數(shù)字信號處理器）。由亞德諾半導體技術有限公司制造生產(chǎn)的ADSP-21375DSP（數(shù)字信號處理器）數(shù)字信號處理器是類似于微處理器或微控制器的器件，但區(qū)別在于其內(nèi)部架構經(jīng)修改，適用于對連續(xù)數(shù)據(jù)流連續(xù)執(zhí)行以乘法和加法運算為主的算法，而不是以條件邏輯或大量并發(fā)進程為主的算法。該器件通常用于諸如音頻或視頻信號處理等應用。

GENERAL DESCRIPTION

The ADSP-21371/ADSP-21375 SHARC? processors are members of the SIMD SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture. The processors are source code compatible with the ADSP-2126x, ADSP-2136x, and ADSP-2116x DSPs, as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. The processors are 32-bit/40-bit floating-point processors optimized for high performance automotive audio applications with their large on-chip SRAM and mask-programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital applications interface (DAI).

SUMMARY

High performance 32-bit/40-bit floating point processor

optimized for high performance audio processing

Single-instruction, multiple-data (SIMD) computational

architecture

On-chip memory, ADSP-21371—1M bits of on-chip SRAM

and 4M bits of on-chip mask-programmable ROM

On-chip memory, ADSP-21375—0.5M bits of on-chip

SRAM and 2M bits of on-chip mask-programmable ROM

Code compatible with all other members of the SHARC family

The ADSP-21371/ADSP-21375 processors are available with a

200/266 MHz core instruction rate with unique

audiocentric peripherals such as the digital applications interface,

S/PDIF transceiver, serial ports, precision clock generators,

and more. For complete ordering information, see

Ordering Guide on Page 52.

DEDICATED AUDIO COMPONENTS

ADSP-21371—S/PDIF-compatible digital audio

receiver/transmitter

ADSP-21371—8 dual data line serial ports that operate at up

to 50 Mbps on each data line — each has a clock, frame

sync, and two data lines that can be configured as either a

receiver or transmitter pair

16 PWM outputs configured as four groups of four outputs

ROM-based security features include

JTAG access to memory permitted with a 64-bit key

Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware

multiplier/divider ratios

Available in a 208-lead LQFP_EP package