ADSP-2184L集成電路（IC）的DSP（數(shù)字信號處理器）規(guī)格書PDF中文資料

ADSP-2184L屬于集成電路（IC）的DSP（數(shù)字信號處理器）。由亞德諾半導體技術(shù)有限公司制造生產(chǎn)的ADSP-2184LDSP（數(shù)字信號處理器）數(shù)字信號處理器是類似于微處理器或微控制器的器件，但區(qū)別在于其內(nèi)部架構(gòu)經(jīng)修改，適用于對連續(xù)數(shù)據(jù)流連續(xù)執(zhí)行以乘法和加法運算為主的算法，而不是以條件邏輯或大量并發(fā)進程為主的算法。該器件通常用于諸如音頻或視頻信號處理等應用。

GENERAL DESCRIPTION

The ADSP-218xL series consists of four single chip microcomputers optimized for digital signal processing applications. The functional block diagram for the ADSP-218xL series members appears in Figure 1 on Page 1. All series members are pin-compatible and are differentiated solely by the amount of on-chip SRAM. This feature, combined with ADSP-21xx code compatibility, provides a great deal of flexibility in the design decision. Specific family members are shown in Table 1.

PERFORMANCE FEATURES

Up to 19 ns instruction cycle time, 52 MIPS sustained performance

Single-cycle instruction execution

Single-cycle context switch

3-bus architecture allows dual operand fetches in every instruction cycle

Multifunction instructions

Power-down mode featuring low CMOS standby power dissipation with 400 CLKIN cycle recovery from power-down condition

Low power dissipation in idle mode

INTEGRATION FEATURES

ADSP-2100 family code compatible (easy to use algebraic syntax), with instruction set extensions

Up to 160K bytes of on-chip RAM, configured Up to 32K words program memory RAM Up to 32K words data memory RAM

Dual-purpose program memory for both instruction and data storage

Independent ALU, multiplier/accumulator, and barrel shifter computational units

2 independent data address generators

Powerful program sequencer provides zero overhead looping conditional instruction execution

Programmable 16-bit interval timer with prescaler 100-lead LQFP and 144-ball BGA

SYSTEM INTERFACE FEATURES

16-bit internal DMA port for high-speed access to on-chip memory (mode selectable)

4M-byte memory interface for storage of data tables and program overlays (mode selectable)

8-bit DMA to byte memory for transparent program and data memory transfers (mode selectable)

Programmable memory strobe and separate I/O memory space permits “glueless” system design

Programmable wait state generation

2 double-buffered serial ports with companding hardware and automatic data buffering

Automatic booting of on-chip program memory from bytewide external memory, for example, EPROM, or through internal DMA Port

6 external interrupts

13 programmable flag pins provide flexible system signaling

UART emulation through software SPORT reconfiguration

ICE-Port emulator interface supports debugging in final systems