ADSP-BF542集成電路（IC）的DSP（數(shù)字信號處理器）規(guī)格書PDF中文資料

ADSP-BF542屬于集成電路（IC）的DSP（數(shù)字信號處理器）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的ADSP-BF542DSP（數(shù)字信號處理器）數(shù)字信號處理器是類似于微處理器或微控制器的器件，但區(qū)別在于其內(nèi)部架構(gòu)經(jīng)修改，適用于對連續(xù)數(shù)據(jù)流連續(xù)執(zhí)行以乘法和加法運(yùn)算為主的算法，而不是以條件邏輯或大量并發(fā)進(jìn)程為主的算法。該器件通常用于諸如音頻或視頻信號處理等應(yīng)用。

GENERAL DESCRIPTION

The ADSP-BF54x Blackfin? processors are members of the Blackfin family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture.

FEATURES

Up to 600 MHz high performance Blackfin processor

Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs

RISC-like register and instruction model

Wide range of operating voltages and flexible booting options

Programmable on-chip voltage regulator

400-ball CSP_BGA, RoHS compliant package

MEMORY

Up to 324K bytes of on-chip memory comprised of

instruction SRAM/cache; dedicated instruction SRAM; data

SRAM/cache; dedicated data SRAM; scratchpad SRAM

External sync memory controller supporting either DDR SDRAM or mobile DDR SDRAM

External async memory controller supporting 8-/16-bit async memories and burst flash devices

NAND flash controller

4 memory-to-memory DMA pairs, 2 with ext. requests

Memory management unit providing memory protection

Code security with Lockbox secure technology and 128-bit AES/ARC4 data encryption

One-time-programmable (OTP) memory

PERIPHERALS

High speed USB On-the-Go (OTG) with integrated PHY

SD/SDIO controller

ATA/ATAPI-6 controller

Up to 4 synchronous serial ports (SPORTs)

Up to 3 serial peripheral interfaces (SPI-compatible)

Up to 4 UARTs, two with automatic H/W flow control

Up to 2 CAN (controller area network) 2.0B interfaces

Up to 2 TWI (2-wire interface) controllers

8- or 16-bit asynchronous host DMA interface

Multiple enhanced parallel peripheral interfaces (EPPIs), supporting ITU-R BT.656 video formats and 18-/24-bit LCD connections

Media transceiver (MXVR) for connection to a MOST network

Pixel compositor for overlays, alpha blending, and color conversion

Up to eleven 32-bit timers/counters with PWM support

Real-time clock (RTC) and watchdog timer

Up/down counter with support for rotary encoder

Up to 152 general-purpose I/O (GPIOs)

On-chip PLL capable of 0.5× to 64× frequency multiplication

Debug/JTAG interface