ADSP-SC595WCBPZ8RL中文資料亞德諾數(shù)據(jù)手冊(cè)PDF規(guī)格書

SYSTEM FEATURES

Dual-enhanced SHARC+ high performance floating-point

cores

Up to 1000 MHz per SHARC+ core

5 Mb (640 kB) L1 SRAM memory per core with parity

(optional ability to configure as cache)

32-bit, 40-bit, and 64-bit floating-point support

32-bit fixed point

Byte, short word, word, long word addressed

Arm Cortex-A55 core

Up to 1200 MHz/3360 DMIPS with advanced SIMD and

floating-point support

32 kB L1 instruction cache with parity/32 kB L1 data cache

with ECC

256 kB L2 cache with ECC

Powerful DMA system with 8 MemDMAs

On-chip memory protection

Integrated safety features

17 mm × 17 mm, 400-ball BGA_ED (0.8 mm pitch),

RoHS compliant

Low system power across automotive temperature range

MEMORY

Large (up to 2 MB) on-chip L2 SRAM with ECC protection

One L3 interface optimized for low system power, providing

16-bit interface to DDR3/DDR3L (supporting 1.35 V

capable DDR3L devices) devices

ADDITIONAL FEATURES

Security and Protection

Cryptographic hardware accelerators

Fast secure boot with IP protection

Supports Arm TrustZone and cryptographic extension

Accelerators

FIR, IIR offload engines