ADSPSC591WCBPZ8RL中文資料亞德諾數(shù)據(jù)手冊PDF規(guī)格書

SYSTEM FEATURES

Dual-enhanced SHARC+ floating-point cores

High performance SHARC+ cores (up to 1 GHz each)

Up to 5 Mb (640 kB) L1 SRAM memory per core with parity

(optional ability to configure as cache)

32-bit, 40-bit, and 64-bit floating-point support

32-bit fixed-point support

Byte, short word, word, and long word addressability

Arm Cortex-A5 core

Up to 1 GHz/1600 DMIPS with NEON/VFPv4-D16

32 kB L1 instruction and data caches with parity

256 kB L2 cache with parity

Powerful DMA system with 8 MemDMAs

On-chip memory protection

Integrated safety features

17 mm × 17 mm, 400-ball BGA_ED (0.8 mm pitch),

RoHS compliant

MEMORY

Large on-chip Level 2 (L2) SRAM with ECC protection, up to

2MB

One Level 3 (L3) interface providing 16-bit interface to

DDR3/ DDR3L SDRAM devices

ADDITIONAL FEATURES

ADSP-2156x pin-compatible package options

Enhanced FIR and IIR accelerators running up to 1 GHz

Security and protection

Cryptographic hardware accelerators

Fast secure boot with IP protection

Support for Arm TrustZone

APPLICATIONS

Automotive: audio amplifier, head unit, ANC/RNC, rear seat

entertainment, digital cockpit, ADAS

Consumer: AVRs, mixing consoles, microphone arrays,

conferencing systems