[AHA]

INTRODUCTION

The AHA4013B is a single chip integrated circuit that implements a high speed Reed-Solomon Forward Error Correction algorithm. The AHA4013B is a member of the AHA PerFEC family of high speed forward error correction (FEC) devices conforming to the Intelsat IESS-308 specification.

FEATURES

HIGH PERFORMANCE

? Polynomial complies to Intelsat IESS-308; RTCA DO-217 Appendix F, Revision D and proposed ITU-TS SG-18 (Formerly CCITT SG-18) standards

? 50 MBytes/sec burst transfer rate with a 50 MHz clock for all block lengths

? Sustained data transfer rate of 12.5 MBytes/sec for block lengths from 54 bytes through 255 bytes using a 50 MHz clock

? Processing latency time less than 12.2 μsec in continuous operation for block lengths of 100 bytes

FLEXIBILITY

? Programmable to correct from 1 to 10 error bytes or 20 erasure bytes per block

? Block lengths programmable from 3 to 255 bytes

? Encode, decode or pass-through capability in line with data flow

? Outputs corrected data or correction vectors in forward or reverse order

? Continuous or burst data transfer

? Programmable error threshold to help determine channel performance

SYSTEM INTERFACE

? Byte wide synchronous I/O ports with internal buffering on both ports

? Dedicated control pins permit discontinuities in system data flow

OTHERS

? 44 pin PLCC; 50 mil lead pitch

? Pin compatible with lower performance AHA4011/12

? Plug compatible with AHA4011/12 except for an initialization register setting

? Software emulation of the algorithm available