AN219528中文資料英飛凌數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Features

Note: In PSoC 61 the Cortex M0+ is reserved for system

functions, and is not available for applications.

32-bit Dual CPU Subsystem

■ 150-MHz Arm? Cortex?-M4F (CM4) CPU with single-cycle

multiply, floating point, and memory protection unit (MPU)

■ 100-MHz Cortex-M0+ (CM0+) CPU with single-cycle multiply

and MPU

■ User-selectable core logic operation at either 1.1 V or 0.9 V

■ Active CPU current slope with 1.1-V core operation

? Cortex-M4: 40 μA/MHz

? Cortex-M0+: 20 μA/MHz

■ Active CPU current slope with 0.9-V core operation

? Cortex-M4: 22 μA/MHz

? Cortex-M0+: 15 μA/MHz

■ Three DMA controllers

Memory Subsystem

■ 512-KB application flash, 32-KB auxiliary flash (AUXflash), and

32-KB supervisory flash (SFlash); read-while-write (RWW)

support. Two 8-KB flash caches, one for each CPU.

■ 256-KB SRAM with programmable power control and retention

granularity

■ One-time-programmable (OTP) 1-Kb eFuse array

Low-Power 1.7-V to 3.6-V Operation

■ Six power modes for fine-grained power management

■ Deep Sleep mode current of 7 μA with 64-KB SRAM retention

■ On-chip DC-DC buck converter, <1 μA quiescent current

■ Backup domain with 64 bytes of memory and real-time clock

Flexible Clocking Options

■ 8-MHz internal main oscillator (IMO) with ±2 accuracy

■ Ultra-low-power 32-kHz internal low-speed oscillator (ILO)

■ On-chip crystal oscillators (16 to 35 MHz, and 32 kHz)

■ Phase-locked loop (PLL) for multiplying clock frequencies

■ Frequency-locked loop (FLL) for multiplying IMO frequency

■ Integer and fractional peripheral clock dividers

Quad-SPI (QSPI)/Serial Memory Interface (SMIF)

■ Execute-In-Place (XIP) from external quad SPI flash

■ On-the-fly encryption and decryption

■ 4-KB cache for greater XIP performance with lower power

■ Supports single, dual, and quad interfaces with throughput up

to 320 Mbps

Segment LCD Drive

■ Supports up to 63 segments and up to 8 commons.

■ Operates in system Deep Sleep mode

Serial Communication

■ Seven run-time configurable serial communication blocks

(SCBs)

? Six SCBs: configurable as SPI, I2C, or UART

? One Deep Sleep SCB: configurable as SPI or I2C

■ USB Full-Speed device interface

■ One SD Host Controller/eMMC/SD controller

■ One CAN FD block

Timing and Pulse-Width Modulation

■ Twelve timer/counter/pulse-width modulators (TCPWMs)

■ Center-aligned, edge, and pseudo-random modes

■ Comparator-based triggering of kill signals

Programmable Analog

■ 12-bit 2-Msps SAR ADC with differential and single-ended

modes and 16-channel sequencer with result averaging

■ Two low-power comparators available in system Deep Sleep

and Hibernate modes

■ Built-in temperature sensor connected to ADC

Up to 64 Programmable GPIOs

■ Two Smart I/O? ports (8 I/Os) enable Boolean operations on

GPIO pins; available during system Deep Sleep

■ Programmable drive modes, strengths, and slew rates

■ Two overvoltage-tolerant (OVT) pins

Capacitive Sensing

■ Cypress CapSense? sigma-delta (CSD) provides best-in-class

signal-to-noise ratio (SNR), liquid tolerance, and proximity

sensing

■ Enables dynamic usage of both self and mutual sensing

■ Automatic hardware tuning (SmartSense?)

Security Built into Platform Architecture

■ Authentication during boot using hardware hashing

■ All debug and test ingress paths can be disabled

■ Up to eight protection contexts

Cryptography Accelerator

■ Hardware acceleration for symmetric and asymmetric

cryptographic methods and hash functions

■ True random number generation (TRNG) function

Packages

■ 100 TQFP, 68 QFN, 49 WLCSP

Device Identification and Revisions

■ Product line ID (12-bit): 0x105

■ Major/Minor die revision ID: 1/2

■ Firmware revisions: ROM Boot: 7.1, Flash Boot: 3.1.0.378 (see

Boot Code section)

This product line has a JTAG ID which is available through the

SWJ interface. It is a 32-bit ID, where:

■ The most significant digit is the device revision, based on the

Major Die Revision

■ The next four digits correspond to the part number, for example

E4B0 as a hexadecimal number

■ The three least significant digits are the manufacturer ID, in this

case 069 as a hexadecimal number

The Silicon ID system call can be used by firmware to get Silicon

ID and ROM Boot data. For more information, see the technical

reference manual (TRM).

The Flash Boot version can be read directly from designated

addresses 0x1600 2004 and 0x1600 2018. For more

information, see the technical reference manual (TRM).