ANX7688中文資料硅谷數(shù)模數(shù)據(jù)手冊PDF規(guī)格書

Features

Standard compliance

- DisplayPort1.4, HDCP2.2/1.4

- MIPI-DSI 1.2 and D-PHY 1.1

DisplayPort Receiver

- DisplayPort1.4 receiver

- Configurable 1, 2 or 4-lane input supports: HBR2.5 (6.75Gbps), HBR2 (5.4Gbps), HBR (2.7Gbps), and RBR (1.62Gbps) data rates

- Horizontal left / right line splitting

- 3D stereo modes

- HDCP2.2 and HDCP1.4 support

Resolution

- DisplayPort Receiver Input Bandwidth supports up to 3600 x 2100 at 60Hz

Single MIPI DSI transmitter interface outputs

- Single MIPI ports per display output

- Display synchronization

- 4-MIPI lanes total per MIPI interface output

- MIPI-DSI data rates up to 1.5 Gbps per lane

3:1 DSC (VESA) on it MIPI Output Transmitters

System operation and power supply

- Slave I2C interface

- 1.0V and 1.8V

I2S Stereo Audio Output

- 2-channels, 192Khz sample rate

- Up to 8-channels TDM

Package: 100-pin BGA, 5mm x 5mm