APW8868B中文資料茂達電子數(shù)據(jù)手冊PDF規(guī)格書

Features

Buck Controller (VDDQ)

· High Input Voltages Range from 3V to 28V Input

Power

· Provide Adjustable Output Voltage from 0.675V to

5.5V +1 Accuracy over Temperature

· Integrated MOSFETDrivers and Bootstrap Forward

P-CHMOSFET

· Low Quiescent Current (200mA)

· Excellent Line and Load Transient Responses

· PFM Mode for Increased Light Load Efficiency

· Constant On-Time Controller Scheme

- Switching Frequency Compensation for PWM

Mode

- Adjustable Switching Frequency from 400kHz to

550kHz in PWM Mode with DC Output Current

· S3 and S5 Pins Control The Device in S0, S3 or S4/

S5 State

· Power Good Monitoring

· 70 Under-Voltage Protection (UVP)

· 125 Over-Voltage Protection (OVP)

· Adjustable Current-Limit Protection

- Using Sense Low-Side MOSFET’s RDS(ON)

· TQFN-20 3mmx3mm Thin package

· Lead Free Available (RoHS Compliant)

+1.5A LDO Section (VTT)

· Sourcing and Sinking Current up to 1.5A

· Fast Transient Response for Output Voltage

· Output Ceramic Capacitors Support at least 10mF

MLCC

· VTT and VTTREF Track at Half the VDDQSNS by

internal divider

· +20mV Accuracy for VTT and VTTREF

· Independent Over-Current Limit (OCL)

· Thermal Shutdown Protection

General Description

TheAPW8868B integrates a synchronous buck PWM controller to generate VDDQ, a sourcing and sinking LDO

linear regulator to generate VTT. It offers the lowest total

solution cost in system where space is at a premium.

The APW8868B provides excellent transient response

and accurate DC voltage output in either PFM or PWM

Mode. In Pulse Frequency Mode (PFM), the APW8868B

provides very high efficiency over light to heavy loads with

loading-modulated switching frequencies. On TQFN-20

Package, the Forced PWM Mode works nearly at constant frequency for low-noise requirements.

The APW8868B is equipped with accurate current-limit,

output under-voltage, and output over-voltage protections.

A Power-On- Reset function monitors the voltage on VCC

prevents wrong operation during power on.

The LDO is designed to provide a regulated voltage with

bi-directional output current for DDR-SDRAM termination.

The device integrates two power transistors to source

and sink current up to 1.5A. It also incorporates currentlimit and thermal shutdown protection.

The output voltage of LDO tracks the voltage at VREF pin.

An internal resistor divider is used to provide a half voltage of VREF for VTTREF and VTT Voltage. The VTT output

voltage is only requiring 20mF of ceramic output capacitance for stability and fast transient response. The S3

and S5 pins provide the sleep state for VTT (S3 state)

and suspend state (S4/S5 state) for device, when S5 and

S3 are both pulled low the device provides the soft-off for

VTT and VTTREF.