AS5C2568DJ-12SLASHXT中文資料AUSTIN數(shù)據(jù)手冊PDF規(guī)格書

GENERAL DESCRIPTION

The Austin Semiconductor SRAM family employs high-speed, low power CMOS designs using a four-transistor memory cell. These SRAMs are fabricated using double-layer metal, double-layer polysilicon technology.

For flexibility in high-speed memory applications, Austin Semiconductor offers chip enable (CE) and output enable (OE) capability. These enhancements can place the outputs in High-Z for additional flexibility in system design.

Writing to these devices is accomplished when write enable (WE) and CE inputs are both LOW. Reading is accomplished when WE remains HIGH and CE and OE go LOW.

The device offers a reduced power standby mode when disabled. This allows system designs to achieve low standby power requirements.

All devices operate from a single +5V power supply and all inputs and outputs are fully TTL compatible.

FEATURES

? Access Times: 12, 15, & 20ns

? Fast output enable (tDOE) for cache applications

? Low active power: 400 mW (TYP)

? Low power standby

? Fully static operation, no clock or refresh required

? High-performance, low-power CMOS double-metal process

? Single +5V (+10%) Power Supply

? Easy memory expansion with CE

? All inputs and outputs are TTL compatible