AS5SS256K36DQ-10/XT中文資料AUSTIN數(shù)據(jù)手冊PDF規(guī)格書

GENERAL DESCRIPTION

The AS5SS256K36 employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process.

This 8Mb Synchronous Burst SRAM integrates a 256K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE), two additional chip enables for easy depth expansion (CE2, CE2), burst control inputs (ADSC, ADSP, ADV), byte write enables (BWx) and global write (GW). Note that CE2 is not available on the A version.

FEATURES

● Organized 256K x 36

● Fast Clock and OE access times

● Single +3.3V +0.3V/-0.165V power supply (VDD)

● SNOOZE MODE for reduced-power standby

● Common data inputs and data outputs

● Individual BYTE WRITE control and GLOBAL WRITE

● Three chip enables for simple depth expansion and address pipelining

● Clock-controlled and registered addresses, data I/Os and control signals

● Internally self-timed WRITE cycle

● Burst control (interleaved or linear burst)

● Automatic power-down for portable applications

● 100-lead TQFP package for high density, high speed

● Low capacitive bus loading