AS7C31026A中文資料ALSC數(shù)據(jù)手冊PDF規(guī)格書

Functional description

The AS7C1026A and AS7C31026A are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 65,536 words × 16 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired.

Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 3/3/4/5 ns are ideal for high-performance applications.

Features

? AS7C1026A (5V version)

? AS7C31026A (3.3V version)

? Industrial and commercial versions

? Organization: 65,536 words × 16 bits

? Center power and ground pins for low noise

? High speed

- 10/12/15/20 ns address access time

- 3/3/4/5 ns output enable access time

? Low power consumption: ACTIVE

- 660 mW (AS7C1026A) / max @ 10 ns

- 324 mW (AS7C31026A) / max @ 10 ns

? Low power consumption: STANDBY

- 55 mW (AS7C1026A) / max CMOS I/O

- 36 mW (AS7C31026A) / max CMOS I/O

? Latest 6T 0.25u CMOS technology

? 2.0V data retention

? Easy memory expansion with CE, OE inputs

? TTL-compatible, three-state I/O

? JEDEC standard packaging

- 44-pin 400 mil SOJ

- 44-pin 400 mil TSOP II

- 48-ball 6 mm × 8 mm CSP mBGA

? ESD protection ≥ 2000 volts

? Latch-up current ≥ 200 mA