AS7C33128PFD36A中文資料ALSC數(shù)據(jù)手冊PDF規(guī)格書

Functional description

The AS7C33128PFD32A and AS7C33128PFD36A are high-performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM) devices organized as 131,072 words × 32 or 36 bits, and incorporate a two-stage register-register pipeline for highest frequency on any given technology.

Features

? Organization: 131,072 words × 32 or 36 bits

? Fast clock speeds to 166 MHz in LVTTL/LVCMOS

? Fast clock to data access: 3.5/3.8/4.0/5.0 ns

? Fast OE access time: 3.5/3.8/4.0/5.0 ns

? Fully synchronous register-to-register operation

? Single register “Flow-through” mode

? Dual-cycle deselect

- Single-cycle deselect also available (AS7C33128PFS32A/AS7C33128PFS36A)

? Pentium?* compatible architecture and timing

? Asynchronous output enable control

? Economical 100-pin TQFP package

? Byte write enables

? Multiple chip enables for easy expansion

? 3.3 core power supply

? 2.5V or 3.3V I/O operation with separate VDDQ

? 30 mW typical standby power in power down mode

? NTD?* pipeline architecture available (AS7C33128KNTD32A/ AS7C33128NTD36A)