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AT45DB041E-SHN2B-Y中文資料etc未分類制造商數(shù)據(jù)手冊PDF規(guī)格書

AT45DB041E-SHN2B-Y
廠商型號

AT45DB041E-SHN2B-Y

功能描述

4-Mbit DataFlash (with Extra 128-Kbits), 1.65V Minimum SPI Serial Flash Memory

文件大小

2.89825 Mbytes

頁面數(shù)量

71

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中文名稱

etc2未分類制造商

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數(shù)據(jù)手冊

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更新時間

2025-2-14 22:59:00

AT45DB041E-SHN2B-Y規(guī)格書詳情

[adesto]

Description

The AT45DB041E is a 1.65V minimum, serial-interface sequential access Flash memory ideally suited for a wide variety of digital voice, image, program code, and data storage applications. The AT45DB041E also supports the RapidS serial interface for applications requiring very high speed operation. Its 4,194,304 bits of memory are organized as 2,048 pages of 256 bytes or 264 bytes each. In addition to the main memory, the AT45DB041E also contains two SRAM buffers of

256/264 bytes each. The buffers allow receiving of data while a page in the main memory is being reprogrammed. Interleaving between both buffers can dramatically increase a systems ability to write a continuous data stream. In addition, the SRAM buffers can be used as additional system scratch pad memory, and EEPROM emulation (bit or byte alterability) can be easily handled with a self-contained three step read-modify-write operation.

Features

Single 1.65V - 3.6V supply

Serial Peripheral Interface (SPI) compatible

? Supports SPI modes 0 and 3

? Supports RapidS? operation

Continuous read capability through entire array

? Up to 85MHz

? Low-power read option up to 15 MHz

? Clock-to-output time (tV) of 6ns maximum

User configurable page size

? 256 bytes per page

? 264 bytes per page (default)

? Page size can be factory pre-configured for 256 bytes

Two fully independent SRAM data buffers (256/264 bytes)

? Allows receiving data while reprogramming the main memory array

Flexible programming options

? Byte/Page Program (1 to 256/264 bytes) directly into main memory

? Buffer Write

? Buffer to Main Memory Page Program

Flexible erase options

? Page Erase (256/264 bytes)

? Block Erase (2KB)

? Sector Erase (64KB)

? Chip Erase (4-Mbits)

Program and Erase Suspend/Resume

Advanced hardware and software data protection features

? Individual sector protection

? Individual sector lockdown to make any sector permanently read-only

128-byte, One-Time Programmable (OTP) Security Register

? 64 bytes factory programmed with a unique identifier

? 64 bytes user programmable

Hardware and software controlled reset options

JEDEC Standard Manufacturer and Device ID Read

Low-power dissipation

? 400nA Ultra-Deep Power-Down current (typical)

? 3μA Deep Power-Down current (typical)

? 25μA Standby current (typical at 20MHz)

? 11mA Active Read current (typical)

Endurance: 100,000 program/erase cycles per page minimum

Data retention: 20 years

Complies with full industrial temperature range

Green (Pb/Halide-free/RoHS compliant) packaging options

? 8-lead SOIC (0.150 wide and 0.208 wide)

? 8-pad Ultra-thin DFN (5 x 6 x 0.6mm)

? 9-ball Ultra-thin UBGA (6 x 6 x 0.6mm)

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