AT45DQ321集成電路（IC）的存儲器規(guī)格書PDF中文資料

Features

Single 2.3V - 3.6V supply

Serial Peripheral Interface (SPI) compatible

Supports SPI modes 0 and 3

Supports RapidS? operation

Supports Dual-input and Quad-input Buffer Write

Supports Dual-output and Quad-output Read

Very high operating frequencies

104MHz (for SPI)

70MHz (for Dual-I/O and Quad-I/O)

Clock-to-output time (tV

) of 7ns maximum

User configurable page size

512 bytes per page

528 bytes per page (default)

Page size can be factory pre-configured for 512 bytes

Two fully independent SRAM data buffers (512/528 bytes)

Allows receiving data while reprogramming the main memory array

Flexible programming options

Byte/Page Program (1 to 512/528 bytes) directly into main memory

Buffer Write

Buffer to Main Memory Page Program

Flexible erase options

Page Erase (512/528 bytes)

Block Erase (4KB)

Sector Erase (64KB)

Chip Erase (32-Mbits)

Program and Erase Suspend/Resume

Advanced hardware and software data protection features

Individual sector protection

Individual sector lockdown to make any sector permanently read-only

128-byte, One-Time Programmable (OTP) Security Register

64 bytes factory programmed with a unique identifier

64 bytes user programmable

Hardware and software controlled reset options

JEDEC Standard Manufacturer and Device ID Read

Low-power dissipation

500nA Ultra-Deep Power-Down current (typical)

3μA Deep Power-Down current (typical)

25μA Standby current (typical)

7mA Active Read current (typical)

Endurance: 100,000 program/erase cycles per page minimum

Data retention: 20 years

Complies with full industrial temperature range

Green (Pb/Halide-free/RoHS compliant) packaging options

8-lead SOIC (0.208 wide)

8-pad Ultra-thin DFN (5 x 6 x 0.6mm)

8-pad Very-thin DFN (6 x 8 x 1.0mm)

Description

The AT45DQ321 is a 2.3V minimum, serial-interface sequential access Flash memory ideally suited for a wide variety of

digital voice, image, program code, and data storage applications. The AT45DQ321 also supports Dual-I/O, Quad-I/O

and the RapidS serial interface for applications requiring very high speed operation. Its 34,603,008 bits of memory are

organized as 8,192 pages of 512 bytes or 528 bytes each. In addition to the main memory, the AT45DQ321 also contains

two SRAM buffers of 512/528 bytes each. The buffers allow receiving of data while a page in the main memory is being

reprogrammed. Interleaving between both buffers can dramatically increase a system's ability to write a continuous data

stream. In addition, the SRAM buffers can be used as additional system scratch pad memory, and E2PROM emulation

(bit or byte alterability) can be easily handled with a self-contained three step read-modify-write operation.

Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the

DataFlash?

uses a serial interface to sequentially access its data. The simple sequential access dramatically reduces

active pin count, facilitates simplified hardware layout, increases system reliability, minimizes switching noise, and

reduces package size. The device is optimized for use in many commercial and industrial applications where highdensity, low-pin count, low-voltage, and low-power are essential.

To allow for simple in-system re-programmability, the AT45DQ321 does not require high input voltages for programming.

The device operates from a single 2.3V to 3.6V power supply for the erase and program and read operations. The

AT45DQ321 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of the Serial

Input (SI), Serial Output (SO), and the Serial Clock (SCK).

All programming and erase cycles are self-timed.