AT89LP2052集成電路（IC）的微控制器規(guī)格書PDF中文資料

Description

The AT89LP2052/LP4052 is a low-power, high-performance CMOS 8-bit microcontroller with 2/4K bytes of In-System Programmable Flash memory. The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set. The AT89LP2052/LP4052 is built around an enhanced CPU core that can fetch a single byte from memory every clock cycle. In the classic 8051 architecture, each fetch required 6 clock cycles, forcing instructions to execute in 12, 24 or 48 clock cycles.

Features

? Compatible with MCS?51 Products

? 20 MIPS Throughput at 20 MHz Clock Frequency and 2.4V, 85°C Operating Conditions

? Single Clock Cycle per Byte Fetch

? 2/4K Bytes of In-System Programmable (ISP) Flash Memory

– Serial Interface for Program Downloading

– 32-byte Fast Page Programming Mode

– 32-byte User Signature Array

? 2.4V to 5.5V VCC Operating Range

? Fully Static Operation: 0 Hz to 20 MHz

? 2-level Program Memory Lock

? 256 x 8 Internal RAM

? Hardware Multiplier

? 15 Programmable I/O Lines

? Configurable I/O with Quasi-bidirectional, Input, Push-pull Output, and

Open-drain Modes

? Enhanced UART with Automatic Address Recognition and Framing Error Detection

? Enhanced SPI with Double-buffered Send/Receive

? Programmable Watchdog Timer with Software Reset

? 4-level Interrupt Priority

? Analog Comparator with Selectable Interrupt and Debouncing

? Two 16-bit Enhanced Timer/Counters with 8-bit PWM

? Brown-out Detector and Power-off Flag

? Internal Power-on Reset

? Low Power Idle and Power-down Modes

? Interrupt Recovery from Power-down Mode