ATF1504ASZ-25JC84中文資料愛特梅爾數(shù)據(jù)手冊PDF規(guī)格書

Description

The ATF1504AS is a high performance, high density Complex Programmable Logic Device (CPLD) which utilizes Atmel’s proven electrically erasable memory technology.

Features

? High Density, High Performance Electrically Erasable Complex Programmable Logic Device

– 64 Macrocells

– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

– 44, 68, 84, 100 pins

– 7 ns Maximum Pin-to-Pin Delay

– Registered Operation Up To 100 MHz

– Enhanced Routing Resources

? In-System Programmability (ISP) via JTAG

? Flexible Logic Macrocell

– D/T/Latch Configurable Flip Flops

– Global and Individual Register Control Signals

– Global and Individual Output Enable

– Programmable Output Slew Rate

– Programmable Output Open Collector Option

– Maximum Logic utilization by burying a register within a COM output

? Advanced Power Management Features

– Automatic 100 μA Stand-By for “Z” Version

– Pin-Controlled 4 mA Stand-By Mode (Typical)

– Programmable Pin-Keeper Inputs and I/Os

– Reduced-Power Feature Per Macrocell

? Available in Commercial and Industrial Temperature Ranges

? Available in 44-, 68-, and 84-pin PLCC; 44- and 100-pin TQFP; and 100-pin PQFP

? Advanced EE Technology

– 100 Tested

– Completely Reprogrammable

– 100 Program/Erase Cycles

– 20 Year Data Retention

– 2000V ESD Protection

– 200 mA Latch-Up Immunity

? JTAG Boundary-Scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

? PCI-compliant

? 3.3 or 5.0V I/O pins

? Security Fuse Feature

Enhanced Features

? Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

? Output Enable Product Terms

? D - Latch Mode

? Combinatorial Output with Registered Feedback within any Macrocell

? Three Global Clock Pins

? ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O

? Fast Registered Input from Product Term

? Programmable “Pin-Keeper” Option

? VCC Power-Up Reset Option

? Pull-Up Option on JTAG Pins TMS and TDI

? Advanced Power Management Features

– Edge Controlled Power Down “L”

– Individual Macrocell Power Option

– Disable ITD on Global Clocks, Inputs and I/O