AV9170中文資料IDT數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

General Description

The AV9170 generates an output clock which is synchronized to a given continuous input clock with zero delay (±1ns at 5V VDD). Using ICS’s proprietary phaselocked loop (PLL) ana-log CMOS technology, the AV9170 is useful for regenerating clocks in high speed systems where skew is a major concern. By the use of the two select pins, multiples or divisions of the input clock can be generated with zero delay (see Tables 2 and 3). The standard versions produce two outputs, where CLK2 is always a divide by two version of CLK1.

Features

? On-chip Phase-Locked Loop for clocks synchronization

? Synchronizes frequencies up to 107 MHz (output) @ 5.0V

? ±1ns skew (max) between input & output clocks @ 5.0V

? Can recover poor duty cycle clocks

? CLK1 to CLK2 skew controlled to within ±1ns @ 5.0V

? 3.0 - 5.5V supply range

? Low power CMOS technology

? Small 8-pin DIP or SOIC package

? On chip loop filter

? AV9170-01, -04 for output clocks 20-107 MHz @ 5.0V, 20 - 66.7 MHz @ 3.3V

? AV9170-02, -05 for output clocks 5-26.75 MHz @ 5.0V, 5 - 16.7 MHz @ 3.3V