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AZ100EL32D+中文資料AZM數(shù)據(jù)手冊(cè)PDF規(guī)格書
AZ100EL32D+規(guī)格書詳情
DESCRIPTION
The AZ10/100EL32 is an integrated ÷2 divider. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of multiple EL32’s in a system.
The EL32 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the device. For single-ended input applications, the VBB reference should be connected to one side of the CLK/CLK ˉˉˉˉ differential input pair. The input signal is then fed to the other CLK/CLK ˉˉˉˉ input. The VBB pin should be used only as a bias for the EL32 as its sink/source capability is limited. When used, the VBB pin should be bypassed to ground via a 0.01μF capacitor.
FEATURES
? 510ps Propagation Delay
? 3.0GHz Toggle Frequency
? High Bandwidth Output Transitions
? 75k? Internal Input Pulldown Resistors
? Direct Replacement for ON Semiconductor MC10EL32 & MC100EL32
產(chǎn)品屬性
- 型號(hào)：
AZ100EL32D+
- 功能描述：
ECL/PECL ÷ 2 Divider
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
ARIZONA |
1227+ |
SOP8 |
574 |
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詢價(jià) | ||
ARIZONA |
21+ |
SOP8 |
574 |
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詢價(jià) | ||
AMI |
01P3 |
SOP |
177 |
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詢價(jià) | ||
24+ |
SMD |
3200 |
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詢價(jià) | |||
ARIZONA |
SOP8 |
68900 |
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詢價(jià) | |||
ARIZONA |
22+ |
SOP8 |
2985 |
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詢價(jià) | ||
N/A |
23+ |
SOP16 |
5000 |
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ARIZONA |
01+ |
28 |
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詢價(jià) | |||
ARIZONA |
22+ |
SOP8 |
43565 |
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詢價(jià) | ||
AMI |
23+ |
NA/ |
5176 |
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詢價(jià) |
