C8051F020開(kāi)發(fā)板套件編程器的評(píng)估板-嵌入式-MCUDSP規(guī)格書(shū)PDF中文資料

SYSTEM OVERVIEW

The C8051F020/1/2/3 devices are fully integrated mixed-signal System-on-a-Chip MCUs with 64 digital I/O pins (C8051F020/2) or 32 digital I/O pins (C8051F021/3). Highlighted features are listed below; refer to Table 1.1 for specific product feature selection.

? High-Speed pipelined 8051-compatible CIP-51 microcontroller core (up to 25 MIPS)

? In-system, full-speed, non-intrusive debug interface (on-chip)

? True 12-bit (C8051F020/1) or 10-bit (C8051F022/3) 100 ksps 8-channel ADC with PGA and analog multiplexer

? True 8-bit ADC 500 ksps 8-channel ADC with PGA and analog multiplexer

? Two 12-bit DACs with programmable update scheduling

? 64k bytes of in-system programmable FLASH memory

? 4352 (4096 + 256) bytes of on-chip RAM

? External Data Memory Interface with 64k byte address space

? SPI, SMBus/I2C, and (2) UART serial interfaces implemented in hardware

? Five general purpose 16-bit Timers

? Programmable Counter/Timer Array with five capture/compare modules

? On-chip Watchdog Timer, VDD Monitor, and Temperature Sensor

ANALOG PERIPHERALS

- SAR ADC

? 12-Bit (C8051F020/1)

? 10-Bit (C8051F022/3)

? ± 1 LSB INL

? Programmable Throughput up to 100 ksps

? Up to 8 External Inputs; Programmable as Single-Ended or Differential

? Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5

? Data-Dependent Windowed Interrupt Generator

? Built-in Temperature Sensor (± 3°C)

- 8-bit ADC

? Programmable Throughput up to 500 ksps

? 8 External Inputs

? Programmable Amplifier Gain: 4, 2, 1, 0.5

- Two 12-bit DACs

? Can Synchronize Outputs to Timers for Jitter-Free Wave form Generation

- Two Analog Comparators

- Voltage Reference

- Precision VDD Monitor/Brown-Out Detector

ON-CHIP JTAG DEBUG & BOUNDARY SCAN

- On-Chip Debug Circuitry Facilitates Full- Speed, Non Intrusive In-Circuit/In-System Debugging

- Provides Breakpoints, Single-Stepping, Watchpoints, Stack Monitor; Inspect/Modify Memory and Registers

- Superior Performance to Emulation Systems Using ICE Chips, Target Pods, and Sockets

- IEEE1149.1 Compliant Boundary Scan

- Low-Cost, Complete Development Kit

HIGH SPEED 8051 μC CORE

- Pipelined Instruction Architecture; Executes 70 of Instruction Set in 1 or 2 System Clocks

- Up to 25 MIPS Throughput with 25 MHz Clock

- 22 Vectored Interrupt Sources

MEMORY

- 4352 Bytes Internal Data RAM (4k + 256)

- 64k Bytes FLASH; In-System programmable in 512-byte Sectors

- External 64k Byte Data Memory Interface (programmable multiplexed or non-multiplexed modes)

DIGITAL PERIPHERALS

- 8 Byte-Wide Port I/O (C8051F020/2); 5V tolerant

- 4 Byte-Wide Port I/O (C8051F021/3); 5V tolerant

- Hardware SMBus? (I2C? Compatible), SPI?, and Two UART Serial Ports Available Concurrently

- Programmable 16-bit Counter/Timer Array with 5 Capture/Compare Modules

- 5 General Purpose 16-bit Counter/Timers

- Dedicated Watch-Dog Timer; Bi-directional Reset Pin

CLOCK SOURCES

- Internal Programmable Oscillator: 2-to-16 MHz

- External Oscillator: Crystal, RC, C, or Clock

- Real-Time Clock Mode using Timer 3 or PCA

SUPPLY VOLTAGE .......................... 2.7V TO 3.6V

- Typical Operating Current: 10 mA @ 20 MHz

- Multiple Power Saving Sleep and Shutdown Modes

100-Pin TQFP and 64-Pin TQFP Packages Available Temperature Range: -40°C to +85°C