CD40175BMS中文資料Intersil數(shù)據(jù)手冊PDF規(guī)格書

Description

CD40175BMS consists of four identical D-type flip-flops. Each flip-flop has an independent DATA D input and complementary Q and Q outputs. The CLOCK and CLEAR inputs are common to all flip-flops. Data are transferred to the Q outputs on the positive going transition of the clock pulse. All four flip-flops are simultaneously reset by a low level on the CLEAR input.

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Features

? High Voltage Type (20V Rating)

? Output Compatible with Two HTL Loads, Two Low Power

??? TTL Loads, or One Low Power Schottky TTL Load

? Functional Equivalent to TTL74175

? 100 Tested for Quiescent Current at 20V

? 5V, 10V and 15V Parametric Ratings

? Maximum Input Current of 1μA at 18V Over Full Package

??? Temperature Range; 100nA at 18V and +25°C

? Noise Margin (Over Full Package/Temperature Range)

??? - 1V at VDD = 5V

??? - 2V at VDD = 10V

??? - 2.5V at VDD = 15V

? Standardized Symmetrical Output Characteristics

? Meets All Requirements of JEDEC Tentative Standard

??? No. 13B, “Standard Specifications for Description of

??? ‘B’ Series CMOS Devices”

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Applications

? Shift Registers

? Buffer/Storage Registers

? Pattern Generators

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