CD40192BMS中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

Features

? CD40192BMS - BCD Type

? CD40193BMS - Binary Type

? High Voltage Type (20V Rating)

? Individual Clock Lines for Counting Up or Counting

Down

? Synchronous High-Speed Carry and Borrow Propagation Delays for Cascading

? Asynchronous Reset and Preset Capability

? Medium Speed Operation

- fCL = 8MHz (typ.) at 10V

? 5V, 10V and 15V Parametric Ratings

? Standardize Symmetrical Output Characteristics

? 100 Tested for Quiescent Current at 20V

? Maximum Input Current of 1?A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC

? Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

? Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Specifications for Description of

‘B’ Series CMOS Devices”

Description

CD40192BMS Presettable BCD Up/Down Counter and the

CD40193BMS Presettable Binary Up/Down Counter each consist of 4 synchronously clocked, gated “D” type flip-flops connected as a counter. The inputs consist of 4 individual jam lines,

a PRESET ENABLE control, individual CLOCK UP and

CLOCK DOWN signals and a master RESET. Four buffered Q

signal outputs as well as CARRY and BORROW outputs for

multiple-stage counting schemes are provided.

The counter is cleared so that all outputs are in a low state by a

high on the RESET line. A RESET is accomplished asynchronously with the clock. Each output is individually programmable

asynchronously with the clock to the level on the corresponding

jam input when the PRESET ENABLE control is low.

The counter counts up one count on the positive clock edge of

the CLOCK UP signal provided the CLOCK DOWN line is high.

The counter counts down one count on the positive clock edge

of the CLOCK DOWN signal provided the CLOCK UP line is

high.

The CARRY and BORROW signals are high when the counter

is counting up or down. The CARRY signal goes low one-half

clock cycle after the counter reaches its maximum count in the

count-up mode. The BORROW signal goes low one-half clock

cycle after the counter reaches its minimum count in the countdown mode. Cascading of multiple packages is easily accomplished without the need for additional external circuitry by tying

the BORROW and CARRY outputs to the CLOCK DOWN and

CLOCK UP inputs, respectively, of the succeeding counter

package.

The CD40192BMS and CD40193BMS are supplied in these

16-lead outline packages:

Braze Seal DIP *H4W, ?H4X

Frit Seal DIP H1F

Ceramic Flatpack *H6P, ?H6W

* CD40192B Only ?CD40193B Only