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CD4021BMS中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

CD4021BMS
廠商型號

CD4021BMS

功能描述

CMOS 8-Stage Static Shift Registers

文件大小

372.81 Kbytes

頁面數(shù)量

9

生產(chǎn)廠商 Renesas Technology Corp
企業(yè)簡稱

RENESAS瑞薩

中文名稱

瑞薩科技有限公司官網(wǎng)

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更新時間

2025-2-10 18:30:00

CD4021BMS規(guī)格書詳情

Features

? High Voltage Types (20V Rating)

? Medium Speed Operation 12MHz (Typ.) Clock Rate at

VDD-VSS = 10V

? Fully Static Operation

? 8 Master-Slave Flip-Flops Plus Output Buffering and

Control Gating

? 100 Tested for Quiescent Current at 20V

? Maximum Input Current of 1?A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC

? Noise Margin (Full Package Temperature Range)

? 1V at VDD = 5V

? 2V at VDD = 10V

? 2.5V at VDD = 15V

? Standardized Symmetrical Output Characteristics

? 5V, 10V and 15V Parametric Ratings

? Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Specifications for Description of

`B' Series CMOS Devices

Description

CD4014BMS -Synchronous Parallel or Serial Input/Serial Output

CD4021BMS -Asynchronous Parallel Input or Synchronous

Serial Input/Serial Output

CD4014BMS and CD4021BMS series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK

and PARALLEL/SERIAL CONTROL inputs, a single SERIAL

data input, and individual parallel “JAM” inputs to each register

stage. Each register stage is a D-type, master-slave flip-flop. In

addition to an output from stage 8, “Q” outputs are also available

from stages 6 and 7. Parallel as well as serial entry is made into

the register synchronously with the positive clock line transition in

the CD4014BMS. In the CD4021BMS serial entry is synchronous with the clock but parallel entry is asynchronous. In both

types, entry is controlled by the PARALLEL/SERIAL CONTROL

input. When the PARALLEL/SERIAL CONTROL input is low,

data is serially shifted into the 8-stage register synchronously

with the positive transition of the clock line. When the PARALLEL/SERIAL CONTROL input is high, data is jammed into the 8-

stage register via the parallel input lines and synchronous with

the positive transition of the clock line. In the CD4021BMS, the

CLOCK input of the internal stage is “forced” when asynchronous parallel entry is made. Register expansion using multiple

packages is permitted.

The CD4014BMS and CD4021BMS are supplied in these 16

lead outline packages:

Braze Seal DIP H4T

Frit Seal DIP H1F

Ceramic Flatpack H6W

供應(yīng)商 型號 品牌 批號 封裝 庫存 備注 價格
TI(德州儀器)
23+
SOIC16
6000
誠信服務(wù),絕對原裝原盤
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TI/德州儀器
24+
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58000
全新原廠原裝正品現(xiàn)貨,可提供技術(shù)支持、樣品免費(fèi)!
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NSC
23+
NA
66
專做原裝正品,假一罰百!
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TI/德州儀器
1535+
480
詢價
TI/德州儀器
23+
SOIC-16
2000
正規(guī)渠道,只有原裝!
詢價
TI
22+
16SOIC
9000
原廠渠道,現(xiàn)貨配單
詢價
TI/德州儀器
23+
16-SOIC
3869
原裝正品代理渠道價格優(yōu)勢
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TI
21+
16SOIC
13880
公司只售原裝,支持實(shí)單
詢價
TexasInstruments
18+
ICSTATICSHFTREG8STG16-SO
6580
公司原裝現(xiàn)貨/歡迎來電咨詢!
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Texas Instruments
23+
16-SO
7300
專注配單,只做原裝進(jìn)口現(xiàn)貨
詢價