CD4046BMS中文資料Intersil數(shù)據(jù)手冊PDF規(guī)格書

Description

CD4046BMS CMOS Micropower Phase-Locked Loop (PLL) consists of a low power linear voltage-controlled oscillator (VCO) and two different phase comparators having a common signal input amplifier and a common comparator input. A 5.2V zener diode is provided for supply regulation if necessary. The CD4046BMS is supplied in these 16-lead outline packages:

Braze Seal DIP H4W

Frit Seal DIP H1F

Ceramic Flatpack H6W

Features

? Very Low Power Consumption: 70μW (typ.) at VCO fo = 10kHz, VDD = 5V

? Operating Frequency Range Up to 1.4 MHz (typ.) at VDD = 10V, RI = 5k?

? Low Frequency Drift: 0.04/oC (typ.) at VDD = 10V

? Choice of Two Phase Comparators:

- Exclusive-OR Network (I)

- Edge-Controlled Memory Network with Phase-Pulse Output for Lock Indication (II)

? High VCO Linearity: <1 (typ.) at VDD = 10V

? VCO Inhibit Control for ON-OFF Keying and Ultra-Low Standby Power Consumption

? Source-Follower Output of VCO Control Input (Demod. Output)

? Zener Diode to Assist Supply Regulation

? Standardize, Symmetrical Output Characteristics

? 100 Tested for Quiescent Current at 20V

? 5V, 10V and 15V Parametric Ratings

? Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”

Applications

? FM Demodulator and Modulator

? Frequency Synthesis and Multiplication

? Frequency Discriminator

? Data Synchronization

? Voltage-to-Frequency Conversion

? Tone Decoding

? FSK - Modems

? Signal Conditioning