CD4070BMS中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

Features

? High Voltage Types (20V Rating)

? CD4070BMS - Quad Exclusive OR Gate

? CD4077BMS - Quad Exclusive NOR Gate

? Medium Speed Operation

- tPHL, tPLH = 65ns (Typ.) at VDD = 10V, CL = 50pF

? 5V, 10V and 15V Parametric Ratings

? Standardized, Symmetrical Output Characteristics

? 100 Tested for Quiescent Current at 20V

? Maximum Input Current of 1?A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC

? Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

? Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Specifications for Description of

‘B’ Series CMOS Devices”

Description

CD4070BMS contains four independent Exclusive OR

gates. The CD4077BMS contains four independent Exclusive NOR gates.

The CD4070BMS and CD4077BMS provide the system

designer with a means for direct implementation of the

Exclusive OR and Exclusive NOR functions, respectively.

The CD4070BMS and CD4077BMS are supplied in these 14

lead outline packages:

Braze Seal DIP H4Q

Frit Seal DIP H1B

Ceramic Flatpack *H4F ?H3W

*CD4070B Only ?CD4077B Only