CD4520BMS中文資料Intersil數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Description

CD4518BMS Dual BCD Up Counter and CD4520BMS Dual Binary Up Counter each consist of two identical, internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or negative-going transition. For single unit operation the ENABLE input is maintained high and the counter advances on each positive-going transition of the CLOCK. The counters are cleared by high levels on their RESET lines.

The counter can be cascaded in the ripple mode by connecting Q4 to the enable input of the subsequent counter while the CLOCK input of the latter is held low.

Features

? High Voltage Types (20V Rating)

? CD4518BMS Dual BCD Up Counter

? CD4520BMS Dual Binary Up Counter

? Medium Speed Operation

?? - 6MHz Typical Clock Frequency at 10V

? Positive or Negative Edge Triggering

? Synchronous Internal Carry Propagation

? 100 Tested for Quiescent Current at 20V

? 5V, 10V and 15V Parametric Ratings

? Maximum Input Current of 1μA at 18V Over Full Package

?? Temperature Range; 100nA at 18V and +25oC

? Noise Margin (Over Full Package/Temperature Range)

?? - 1V at VDD = 5V

?? - 2V at VDD = 10V

?? - 2.5V at VDD = 15V

? Standardized Symmetrical Output Characteristics

? Meets All Requirements of JEDEC Tentative Standard

?? No. 13B, “Standard Specifications for Description of

?? ‘B’ Series CMOS Devices”

Applications

? Multistage Synchronous Counting

? Multistage Ripple Counting

? Frequency Dividers