CD54HC112F3A中文資料德州儀器數(shù)據(jù)手冊PDF規(guī)格書

1 Features

? Hysteresis on clock inputs for improved noise

immunity and increased input rise and fall times

? Asynchronous set and reset

? Complementary outputs

? Buffered inputs

? Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA

= 25℃

? Fanout (over temperature range)

– Standard outputs: 10 LSTTL loads

– Bus driver outputs: 15 LSTTL loads

? Wide operating temperature range: -55℃ to 125℃

? Balanced propagation delay and transition times

? Significant power reduction compared to LSTTL

Logic ICs

? HC types

– 2 V to 6 V operation

– High noise immunity: NIL = 30, NIH = 30 of

VCC at VCC = 5 V

? HCT types

– 4.5 V to 5.5 V operation

– Direct LSTTL input logic compatibility, VIL = 0.8

V (max), VIH = 2 V (min)

– CMOS input compatibility, II ≤ 1 μA at VOL, VOH

2 Description

The ’HC112 and ’HCT112 utilize silicon-gate CMOS

technology to achieve operating speeds equivalent to

LSTTL parts. They exhibit the low power consumption

of standard CMOS integrated circuits, together with

the ability to drive 10 LSTTL loads.

These flip-flops have independent J, K, PRE, CLR,

and Clock inputs and Q and Q outputs. They

change state on the negative-going transition of

the clock pulse. PRE and CLR are accomplished

asynchronously by low-level inputs.

The HCT logic family is functionally as well as pin

compatible with the standard LS logic family.