CDCDB803RSLR集成電路（IC）的時(shí)鐘緩沖器驅(qū)動(dòng)器規(guī)格書PDF中文資料

CDCDB803RSLR屬于集成電路（IC）的時(shí)鐘緩沖器驅(qū)動(dòng)器。由德州儀器制造生產(chǎn)的CDCDB803RSLR時(shí)鐘緩沖器，驅(qū)動(dòng)器時(shí)鐘緩沖器和驅(qū)動(dòng)器集成電路產(chǎn)品族中的產(chǎn)品用于幫助信號(hào)在系統(tǒng)中傳輸，常用作頻率/時(shí)間參考信號(hào)，以同步系統(tǒng)內(nèi)的活動(dòng)。盡管這些器件最常用到的功能就是緩沖（即，為使信號(hào)不受驅(qū)動(dòng)負(fù)載的影響而從某個(gè)信號(hào)源復(fù)制信號(hào)），但是該產(chǎn)品族中的某些器件還能執(zhí)行其他功能，例如選擇性改變緩沖信號(hào)路徑、按某個(gè)整數(shù)值分割信號(hào)頻率，或進(jìn)行所用電信號(hào)格式轉(zhuǎn)換。

1 Features

? 8 LP-HCSL outputs with programmable integrated

85-Ω (default) or 100-Ω differential output

terminations

? 8 hardware output enable (OE#) controls

? Additive phase jitter after PCIE Gen 6 filter: 20 fs,

RMS (maximum)

? Additive phase jitter after PCIE Gen 5 filter: 25 fs,

RMS (maximum)

? Additive phase jitter after DB2000Q filter: 38 fs,

RMS (maximum)

? Supports Common Clock (CC) and Individual

Reference (IR) architectures

– Spread spectrum-compatible

? Output-to-output skew: < 50 ps

? Input-to-output delay: < 3 ns

? Fail-safe input

? Programmable output slew rate control

? 9 selectable SMBus addresses

? 3.3-V core and IO supply voltages

? Hardware-controlled low power mode (PD#)

? Current consumption: 72 mA maximum

? 6-mm × 6-mm, 48-pin VQFN package

2 Applications

? Microserver & tower server

? Storage area network & host bus adapter card

? Network attached storage

? Hardware accelerator

? Rack server

3 Description

The CDCDB803 is a 8-output LP-HCSL, DB800ZLcompliant,

clock buffer capable of distributing the

reference clock for PCIe Gen 1-6, QuickPath

Interconnect (QPI), UPI, SAS, and SATA interfaces.

The SMBus interface and eight output enable pins

allow the configuration and control of all eight

outputs individually. The CDCDB803 is a DB800ZL

derivative buffer and meets or exceeds the system

parameters in the DB800ZL specification. It also

meets or exceeds the parameters in the DB2000Q

specification. The CDCDB803 is packaged in a 6-mm

× 6-mm, 48-pin VQFN package.