CDP1802ACD3中文資料Intersil數(shù)據(jù)手冊PDF規(guī)格書

The CDP1802A/3 High-Reliability LSI CMOS 8-bit register oriented Central-Processing Unit (CPU) is designed for use as a general purpose computing or control element in a wide range of stored-program systems or products.

The CDP1802A/3 includes all of the circuits required for fetching, interpreting, and executing instructions which have been stored in standard types of memories. Extensive input/output (I/O) control features are also provided to facilitate system design.

The 1800 Series Architecture is designed with emphasis on the total microcomputer system as an integral entity so that systems having maximum flexibility and minimum cost can be realized. The 1800 Series CPU also provides a synchronous interface to memories and external controllers for I/O devices, and minimizes the cost of interface controllers. Further, the I/O interface is capable of supporting devices operating in polled, interrupt-driven, or direct memory-access modes.

Features

For Use In Aerospace, Military, and Critical Industrial Equipment

? Minimum Instruction Fetch-Execute Time of 4.5μs

(Maximum Clock Frequency of 3.6MHz) at VDD = 5V, TA = +25°C

? Operation Over the Full Military

Temperature Range . . . . . . . . . . . . . . . -55°C to +125°C

? Any Combination of Standard RAM and ROM Up to

65,536 Bytes

? 8-Bit Parallel Organization With Bi-directional Data

Bus and Multiplexed Address Bus

? 16x16 Matrix of Registers for Use as Multiple Program

Counters, Data Pointers, or Data Registers

? On-Chip DMA, Interrupt, and Flag Inputs

? High Noise Immunity . . . . . . . . . . . . . . . . . . 30 of VDD

? Pb-Free (RoHS compliant)