CDP1854ACD中文資料Intersil數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Description

The CDP1854A and CDP1854AC are silicon-gate CMOS Universal Asynchronous Receiver/Transmitter (UART) circuits. They are designed to provide the necessary formatting and control for interfacing between serial and parallel data. For example, these UARTs can be used to interface between a peripheral or terminal with serial I/O ports and the 8-bit CDP1800-series microprocessor parallel data bus system. The CDP1854A is capable of full duplex operation, i.e., simultaneous conversion of serial input data to parallel output data and parallel input data to serial output data.

Features

? Two Operating Modes

??? - Mode 0 - Functionally Compatible with Industry Types Such as the TR1602A and CDP6402

??? - Mode 1 - Interfaces Directly with CDP1800-Series Microprocessors without Additional Components

? Full or Half Duplex Operation

? Parity, Framing and Overrun Error Detection

? Baud Rate

??? - DC to 200K Bits/s at VDD . . . . . . . . . . . . . . . . . . . . 5V

??? - DC to 400K Bits/s at VDD . . . . . . . . . . . . . . . . . . . . 10V

? Fully Programmable with Externally Selectable Word Length (5-8 Bits), Parity Inhibit, Even/Odd Parity, and 1, 1-1/2, or 2 Stop Bits

? False Start Bit Detection